WCET-based comparison of an instruction scratchpad and a method cache

Jack Whitham; Martin Schoeberl

doi:10.1109/ISORC.2014.48

WCET-based comparison of an instruction scratchpad and a method cache

Jack Whitham, Martin Schoeberl

University of York

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

286 Downloads (Pure)

Abstract

This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.

Original language	English
Title of host publication	2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)
Editors	Lisa O'Connor
Publisher	IEEE
Publication date	2014
Pages	301-308
ISBN (Print)	978-1-4799-4430-9
DOIs	https://doi.org/10.1109/ISORC.2014.48
Publication status	Published - 2014
Event	17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC - Peppermill Resort, Reno, Nevada, United States Duration: 10 Jun 2014 → 12 Jun 2014 Conference number: 17 https://www.isorc2014.org/

Conference

Conference	17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC
Number	17
Location	Peppermill Resort
Country/Territory	United States
City	Reno, Nevada
Period	10/06/2014 → 12/06/2014
Internet address	https://www.isorc2014.org/

Series	International Symposium on Object-Oriented Real-Time Distributed Computing
ISSN	1555-0885

Bibliographical note

2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Access to Document

10.1109/ISORC.2014.48

SpmvsmcAccepted author manuscript, 158 KB

OpenUrl availability

Full text

Cite this

@inproceedings{b6ca85ad5bd24c0b93cdb9cb085f653b,

title = "WCET-based comparison of an instruction scratchpad and a method cache",

abstract = "This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.",

author = "Jack Whitham and Martin Schoeberl",

note = "2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.; 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC, ISORC 2014 ; Conference date: 10-06-2014 Through 12-06-2014",

year = "2014",

doi = "10.1109/ISORC.2014.48",

language = "English",

isbn = "978-1-4799-4430-9",

series = "International Symposium on Object-Oriented Real-Time Distributed Computing",

pages = "301--308",

editor = "Lisa O'Connor",

booktitle = "2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)",

publisher = "IEEE",

address = "United States",

url = "https://www.isorc2014.org/",

}

Whitham, J & Schoeberl, M 2014, WCET-based comparison of an instruction scratchpad and a method cache. in L O'Connor (ed.), 2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC). IEEE, International Symposium on Object-Oriented Real-Time Distributed Computing, pp. 301-308, 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC, Reno, Nevada, United States, 10/06/2014. https://doi.org/10.1109/ISORC.2014.48

WCET-based comparison of an instruction scratchpad and a method cache. / Whitham, Jack; Schoeberl, Martin.
2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC). ed. / Lisa O'Connor. IEEE, 2014. p. 301-308 (International Symposium on Object-Oriented Real-Time Distributed Computing).

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - WCET-based comparison of an instruction scratchpad and a method cache

AU - Whitham, Jack

AU - Schoeberl, Martin

N1 - Conference code: 17

PY - 2014

Y1 - 2014

N2 - This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.

AB - This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.

U2 - 10.1109/ISORC.2014.48

DO - 10.1109/ISORC.2014.48

M3 - Article in proceedings

SN - 978-1-4799-4430-9

T3 - International Symposium on Object-Oriented Real-Time Distributed Computing

SP - 301

EP - 308

BT - 2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)

A2 - O'Connor, Lisa

PB - IEEE

T2 - 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC

Y2 - 10 June 2014 through 12 June 2014

ER -

WCET-based comparison of an instruction scratchpad and a method cache

Abstract

Conference

Bibliographical note

Access to Document

OpenUrl availability

Fingerprint

Cite this