This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worst-case execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.
|Title of host publication||2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)|
|Publication status||Published - 2014|
|Event||17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC - Peppermill Resort, Reno, Nevada, United States|
Duration: 10 Jun 2014 → 12 Jun 2014
Conference number: 17
|Conference||17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC|
|Period||10/06/2014 → 12/06/2014|
|Series||International Symposium on Object-Oriented Real-Time Distributed Computing|
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Whitham, J., & Schoeberl, M. (2014). WCET-based comparison of an instruction scratchpad and a method cache. In L. O'Connor (Ed.), 2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) (pp. 301-308). IEEE. International Symposium on Object-Oriented Real-Time Distributed Computing https://doi.org/10.1109/ISORC.2014.48