Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer

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Abstract

This paper presents a fabrication process of a Poly-Silicon-On-Insulator (PSOI) wafer that can be used as an alternative to conventional Silicon-On-Insulator (SOI) wafers for fabrication of Capacitative Micromachined Ultrasound Transducers (CMUT). The fabrication of PSOI wafers does, unlike the conventional SOI fabrication, not involve any bonding steps. A batch of PSOI wafers having a 400 nm BOX layer and a 2.6 µm ± 0.04 µm (1σ) device layer is fabricated and characterized. A surface roughness of 0.47 nm is measured for the PSOI device layer, and successful fusion bonds (direct bonds) are demonstrated between PSOI wafers and oxidized silicon wafers. A wafer-bonded CMUT using a PSOI wafer is fabricated and electrically characterized, and the expected CMUT performance is observed. Impedance spectra are demonstrated at five different DC biases, the expected spring softening effect is observed when the magnitude of the DC bias is increased.
Original languageEnglish
Title of host publicationProceedings of the 2019 IEEE International Ultrasonics Symposium
PublisherIEEE
Publication date2019
Pages758-761
ISBN (Electronic)978-1-7281-4596-9
DOIs
Publication statusPublished - 2019
Event2019 IEEE International Ultrasonics Symposium - SEC Glasgow, Glasgow, United Kingdom
Duration: 6 Oct 20199 Oct 2019
http://attend.ieee.org/ius-2019/

Conference

Conference2019 IEEE International Ultrasonics Symposium
LocationSEC Glasgow
CountryUnited Kingdom
CityGlasgow
Period06/10/201909/10/2019
Internet address

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