Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer

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Abstract

This paper presents a fabrication process of a Poly-Silicon-On-Insulator (PSOI) wafer that can be used as an alternative to conventional Silicon-On-Insulator (SOI) wafers for fabrication of Capacitative Micromachined Ultrasound Transducers (CMUT). The fabrication of PSOI wafers does, unlike the conventional SOI fabrication, not involve any bonding steps. A batch of PSOI wafers having a 400 nm BOX layer and a 2.6 µm ± 0.04 µm (1σ) device layer is fabricated and characterized. A surface roughness of 0.47 nm is measured for the PSOI device layer, and successful fusion bonds (direct bonds) are demonstrated between PSOI wafers and oxidized silicon wafers. A wafer-bonded CMUT using a PSOI wafer is fabricated and electrically characterized, and the expected CMUT performance is observed. Impedance spectra are demonstrated at five different DC biases, the expected spring softening effect is observed when the magnitude of the DC bias is increased.
Original languageEnglish
Title of host publicationProceedings of the 2019 IEEE International Ultrasonics Symposium
PublisherIEEE
Publication date2019
Pages758-761
ISBN (Electronic)978-1-7281-4596-9
DOIs
Publication statusPublished - 2019
Event2019 IEEE International Ultrasonics Symposium - SEC Glasgow, Glasgow, United Kingdom
Duration: 6 Oct 20199 Oct 2019
http://attend.ieee.org/ius-2019/

Conference

Conference2019 IEEE International Ultrasonics Symposium
LocationSEC Glasgow
CountryUnited Kingdom
CityGlasgow
Period06/10/201909/10/2019
Internet address

Cite this

@inproceedings{3bda001c76644ad6b34d54fe1827ae3e,
title = "Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer",
abstract = "This paper presents a fabrication process of a Poly-Silicon-On-Insulator (PSOI) wafer that can be used as an alternative to conventional Silicon-On-Insulator (SOI) wafers for fabrication of Capacitative Micromachined Ultrasound Transducers (CMUT). The fabrication of PSOI wafers does, unlike the conventional SOI fabrication, not involve any bonding steps. A batch of PSOI wafers having a 400 nm BOX layer and a 2.6 µm ± 0.04 µm (1σ) device layer is fabricated and characterized. A surface roughness of 0.47 nm is measured for the PSOI device layer, and successful fusion bonds (direct bonds) are demonstrated between PSOI wafers and oxidized silicon wafers. A wafer-bonded CMUT using a PSOI wafer is fabricated and electrically characterized, and the expected CMUT performance is observed. Impedance spectra are demonstrated at five different DC biases, the expected spring softening effect is observed when the magnitude of the DC bias is increased.",
author = "Havreland, {Andreas Spandet} and Mathias Engholm and Grass, {Rune Sixten} and Jensen, {J{\o}rgen Arendt} and Thomsen, {Erik Vilain}",
year = "2019",
doi = "10.1109/ULTSYM.2019.8925931",
language = "English",
pages = "758--761",
booktitle = "Proceedings of the 2019 IEEE International Ultrasonics Symposium",
publisher = "IEEE",
address = "United States",

}

Havreland, AS, Engholm, M, Grass, RS, Jensen, JA & Thomsen, EV 2019, Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer. in Proceedings of the 2019 IEEE International Ultrasonics Symposium. IEEE, pp. 758-761, 2019 IEEE International Ultrasonics Symposium, Glasgow, United Kingdom, 06/10/2019. https://doi.org/10.1109/ULTSYM.2019.8925931

Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer. / Havreland, Andreas Spandet; Engholm, Mathias; Grass, Rune Sixten; Jensen, Jørgen Arendt; Thomsen, Erik Vilain.

Proceedings of the 2019 IEEE International Ultrasonics Symposium. IEEE, 2019. p. 758-761.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

TY - GEN

T1 - Wafer bonded CMUT technology utilizing a Poly-Silicon-on-Insulator wafer

AU - Havreland, Andreas Spandet

AU - Engholm, Mathias

AU - Grass, Rune Sixten

AU - Jensen, Jørgen Arendt

AU - Thomsen, Erik Vilain

PY - 2019

Y1 - 2019

N2 - This paper presents a fabrication process of a Poly-Silicon-On-Insulator (PSOI) wafer that can be used as an alternative to conventional Silicon-On-Insulator (SOI) wafers for fabrication of Capacitative Micromachined Ultrasound Transducers (CMUT). The fabrication of PSOI wafers does, unlike the conventional SOI fabrication, not involve any bonding steps. A batch of PSOI wafers having a 400 nm BOX layer and a 2.6 µm ± 0.04 µm (1σ) device layer is fabricated and characterized. A surface roughness of 0.47 nm is measured for the PSOI device layer, and successful fusion bonds (direct bonds) are demonstrated between PSOI wafers and oxidized silicon wafers. A wafer-bonded CMUT using a PSOI wafer is fabricated and electrically characterized, and the expected CMUT performance is observed. Impedance spectra are demonstrated at five different DC biases, the expected spring softening effect is observed when the magnitude of the DC bias is increased.

AB - This paper presents a fabrication process of a Poly-Silicon-On-Insulator (PSOI) wafer that can be used as an alternative to conventional Silicon-On-Insulator (SOI) wafers for fabrication of Capacitative Micromachined Ultrasound Transducers (CMUT). The fabrication of PSOI wafers does, unlike the conventional SOI fabrication, not involve any bonding steps. A batch of PSOI wafers having a 400 nm BOX layer and a 2.6 µm ± 0.04 µm (1σ) device layer is fabricated and characterized. A surface roughness of 0.47 nm is measured for the PSOI device layer, and successful fusion bonds (direct bonds) are demonstrated between PSOI wafers and oxidized silicon wafers. A wafer-bonded CMUT using a PSOI wafer is fabricated and electrically characterized, and the expected CMUT performance is observed. Impedance spectra are demonstrated at five different DC biases, the expected spring softening effect is observed when the magnitude of the DC bias is increased.

U2 - 10.1109/ULTSYM.2019.8925931

DO - 10.1109/ULTSYM.2019.8925931

M3 - Article in proceedings

SP - 758

EP - 761

BT - Proceedings of the 2019 IEEE International Ultrasonics Symposium

PB - IEEE

ER -