VLSI implementation of a fairness ATM buffer system

J.V. Nielsen, Lars Dittmann, Jens Kargaard Madsen, Peter Stuhr Lassen

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    Abstract

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component
    Original languageEnglish
    Title of host publicationConference Record of IEEE International Conference on Communications : Converging Technologies for Tomorrow's Applications
    VolumeVolume 2
    PublisherIEEE
    Publication date1996
    Pages681-686
    ISBN (Print)07-80-33250-4
    DOIs
    Publication statusPublished - 1996
    EventIEEE International Conference on Communications 1996 - Dallas, United States
    Duration: 23 Jun 199627 Jun 1996

    Conference

    ConferenceIEEE International Conference on Communications 1996
    Country/TerritoryUnited States
    CityDallas
    Period23/06/199627/06/1996

    Bibliographical note

    Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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