VLSI implementation of a fairness ATM buffer system

J.V. Nielsen; Lars Dittmann; Jens Kargaard Madsen; Peter Stuhr Lassen

doi:10.1109/ICC.1996.541268

VLSI implementation of a fairness ATM buffer system

J.V. Nielsen, Lars Dittmann, Jens Kargaard Madsen, Peter Stuhr Lassen

Technical University of Denmark

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component

Original language	English
Title of host publication	Conference Record of IEEE International Conference on Communications : Converging Technologies for Tomorrow's Applications
Volume	Volume 2
Publisher	IEEE
Publication date	1996
Pages	681-686
ISBN (Print)	07-80-33250-4
DOIs	https://doi.org/10.1109/ICC.1996.541268
Publication status	Published - 1996
Event	IEEE International Conference on Communications 1996 - Dallas, United States Duration: 23 Jun 1996 → 27 Jun 1996

Conference

Conference	IEEE International Conference on Communications 1996
Country/Territory	United States
City	Dallas
Period	23/06/1996 → 27/06/1996

Bibliographical note

Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "VLSI implementation of a fairness ATM buffer system",

abstract = "This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component",

author = "J.V. Nielsen and Lars Dittmann and Madsen, {Jens Kargaard} and Lassen, {Peter Stuhr}",

note = "Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; IEEE International Conference on Communications 1996, ICC 1996 ; Conference date: 23-06-1996 Through 27-06-1996",

year = "1996",

doi = "10.1109/ICC.1996.541268",

language = "English",

isbn = "07-80-33250-4",

volume = "Volume 2",

pages = "681--686",

booktitle = "Conference Record of IEEE International Conference on Communications",

publisher = "IEEE",

address = "United States",

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Nielsen, JV, Dittmann, L, Madsen, JK & Lassen, PS 1996, VLSI implementation of a fairness ATM buffer system. in Conference Record of IEEE International Conference on Communications: Converging Technologies for Tomorrow's Applications. vol. Volume 2, IEEE, pp. 681-686, IEEE International Conference on Communications 1996, Dallas, Texas, United States, 23/06/1996. https://doi.org/10.1109/ICC.1996.541268

VLSI implementation of a fairness ATM buffer system. / Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard et al.
Conference Record of IEEE International Conference on Communications: Converging Technologies for Tomorrow's Applications. Vol. Volume 2 IEEE, 1996. p. 681-686.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AU - Dittmann, Lars

AU - Madsen, Jens Kargaard

AU - Lassen, Peter Stuhr

N1 - Copyright: 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1996

Y1 - 1996

N2 - This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component

AB - This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component

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DO - 10.1109/ICC.1996.541268

M3 - Article in proceedings

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SP - 681

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BT - Conference Record of IEEE International Conference on Communications

PB - IEEE

T2 - IEEE International Conference on Communications 1996

Y2 - 23 June 1996 through 27 June 1996

ER -

VLSI implementation of a fairness ATM buffer system

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