VLSI implementation of a fairness ATM buffer system

J.V. Nielsen, Lars Dittmann, Jens Kargaard Madsen, Peter Stuhr Lassen

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    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated with a model feasible for practical implementation. This approximated model has been implemented as a VLSI component
    Original languageEnglish
    Title of host publicationConference Record of IEEE International Conference on Communications : Converging Technologies for Tomorrow's Applications
    VolumeVolume 2
    Publication date1996
    ISBN (Print)07-80-33250-4
    Publication statusPublished - 1996
    EventIEEE International Conference on Communications 1996 - Dallas, United States
    Duration: 23 Jun 199627 Jun 1996


    ConferenceIEEE International Conference on Communications 1996
    Country/TerritoryUnited States

    Bibliographical note

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