VHF Series-Input Parallel-Output Interleaved Self-Oscillating Resonant SEPIC Converter

Milovan Kovacevic; Arnold Knott; Michael A. E. Andersen

doi:10.1109/ECCE.2013.6646959

VHF Series-Input Parallel-Output Interleaved Self-Oscillating Resonant SEPIC Converter

Milovan Kovacevic, Arnold Knott, Michael A. E. Andersen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

If the switches of two resonant SEPIC converters are capacitively coupled, it is possible to obtain a self-oscillating converter in which the two power stages operate in interleaved mode. This paper describes a topology where the inputs of two SEPIC converters are connected in series, thereby sharing the input voltage. For the same output power and switching frequency, the voltage stress of the switches is reduced by a factor of two while the voltage transformation ratio is doubled. This modification is possible with addition of only two capacitors in the power stage and a biasing circuit. Design considerations and challenges are investigated. To verify the proposed design, a 70 V input, 37 MHz prototype was built using low-cost switching and passive components, and experimental results are presented. Peak observed efficiency was 82%.

Original language	English
Title of host publication	Proceedings of ECCE USA 2013
Publisher	IEEE
Publication date	2013
Pages	2052-2056
ISBN (Print)	978-1-4799-0336-8
DOIs	https://doi.org/10.1109/ECCE.2013.6646959
Publication status	Published - 2013
Event	IEEE ECCE USA 2013 - Denver, Colorado, United States Duration: 15 Sept 2013 → 19 Sept 2013 http://www.ecce2013.org/

Conference

Conference	IEEE ECCE USA 2013
Country/Territory	United States
City	Denver, Colorado
Period	15/09/2013 → 19/09/2013
Internet address	http://www.ecce2013.org/

Keywords

Power
Energy and Industry Applications
Capacitance
Frequency conversion;
Inverters
Logic gates
MOSFET
Topology
Voltage measurement

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title = "VHF Series-Input Parallel-Output Interleaved Self-Oscillating Resonant SEPIC Converter",

abstract = "If the switches of two resonant SEPIC converters are capacitively coupled, it is possible to obtain a self-oscillating converter in which the two power stages operate in interleaved mode. This paper describes a topology where the inputs of two SEPIC converters are connected in series, thereby sharing the input voltage. For the same output power and switching frequency, the voltage stress of the switches is reduced by a factor of two while the voltage transformation ratio is doubled. This modification is possible with addition of only two capacitors in the power stage and a biasing circuit. Design considerations and challenges are investigated. To verify the proposed design, a 70 V input, 37 MHz prototype was built using low-cost switching and passive components, and experimental results are presented. Peak observed efficiency was 82%.",

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N2 - If the switches of two resonant SEPIC converters are capacitively coupled, it is possible to obtain a self-oscillating converter in which the two power stages operate in interleaved mode. This paper describes a topology where the inputs of two SEPIC converters are connected in series, thereby sharing the input voltage. For the same output power and switching frequency, the voltage stress of the switches is reduced by a factor of two while the voltage transformation ratio is doubled. This modification is possible with addition of only two capacitors in the power stage and a biasing circuit. Design considerations and challenges are investigated. To verify the proposed design, a 70 V input, 37 MHz prototype was built using low-cost switching and passive components, and experimental results are presented. Peak observed efficiency was 82%.

AB - If the switches of two resonant SEPIC converters are capacitively coupled, it is possible to obtain a self-oscillating converter in which the two power stages operate in interleaved mode. This paper describes a topology where the inputs of two SEPIC converters are connected in series, thereby sharing the input voltage. For the same output power and switching frequency, the voltage stress of the switches is reduced by a factor of two while the voltage transformation ratio is doubled. This modification is possible with addition of only two capacitors in the power stage and a biasing circuit. Design considerations and challenges are investigated. To verify the proposed design, a 70 V input, 37 MHz prototype was built using low-cost switching and passive components, and experimental results are presented. Peak observed efficiency was 82%.

KW - Power

KW - Energy and Industry Applications

KW - Capacitance

KW - Frequency conversion;

KW - Inverters

KW - Logic gates

KW - MOSFET

KW - Topology

KW - Voltage measurement

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VHF Series-Input Parallel-Output Interleaved Self-Oscillating Resonant SEPIC Converter

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