Verification of Chisel Hardware designs with ChiselVerify

Andrew Dobis*, Kevin Laeufer, Hans Jakob Damsgaard, Tjark Petersen, Kasper Juul Hesse Rasmussen, Enrico Tolotto, Simon Thye Andersen, Richard Lin, Martin Schoeberl

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

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With the current ever-increasing demand for performance, hardware developers find themselves turning ever-more towards the construction of application-specific accelerators to achieve higher performance and lower energy consumption. In order to meet the ever-shortening time constraints, both hardware development and verification tools need to be improved.
Chisel, as a hardware construction language, tackles this problem by speeding up the development of digital designs. However, the Chisel infrastructure lacks tools for verification. This paper improves the efficiency of verification in Chisel by proposing methods to support both formal and dynamic verification of digital designs in Scala. It builds on top of ChiselTest, the official testing framework for Chisel. Our work supports functional coverage, constrained random verification, bus functional models, and transaction-level modeling in a verification library named ChiselVerify, while the formal methods are directly integrated into Chisel3.
Original languageEnglish
Article number104737
JournalMicroprocessors and Microsystems
Number of pages19
Publication statusPublished - 2023
Event2021 IEEE Nordic Circuits and Systems Conference - Virtuel event, Oslo, Norway
Duration: 26 Oct 202127 Oct 2021


Conference2021 IEEE Nordic Circuits and Systems Conference
LocationVirtuel event
Internet address


  • Chisel
  • Digital design
  • Scala
  • Verification


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