Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors

Alberto Nannarelli*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

The increasing demand of computation at the edge and the tight power budgets push designers to migrate double and single-precision calculations to formats of reduced precision and dynamic range for applications that can tolerate some inaccuracy.In this context, we introduce a variable format for reduced precision floating-point with storage limited to 16 bits. This format is suitable for applications in signal processing, machine learning and other applications in embedded systems. We present the hardware implementations for multiplication and division units that can sustain a throughput of one result per clock cycle designed for vector processing. We also show some examples of applications that can benefit from the proposed format.

Original languageEnglish
Title of host publicationProceedings of 2020 IEEE 27th Symposium on Computer Arithmetic
PublisherIEEE
Publication dateJun 2020
Pages96-102
Article number9154490
ISBN (Electronic)9781728171203
DOIs
Publication statusPublished - Jun 2020
Event27th IEEE Symposium on Computer Arithmetic - Portland, United States
Duration: 7 Jun 202010 Jun 2020

Conference

Conference27th IEEE Symposium on Computer Arithmetic
CountryUnited States
CityPortland
Period07/06/202010/06/2020

Keywords

  • Customizable bias
  • Floating-point
  • Variable precision

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