Two-Step Register Allocation for Implementing Single-Path Code

Emad Jacob Maroun, Martin Schoeberl, Peter Puschner

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

Register allocation is a crucial step in the compilation pipeline that decides what program values occupy which physical registers. Single-path code’s use of predicated instructions instead of branching control-flow means register allocation must also allocate predicate registers. In this paper, we improve the original single-path transformation to allow generic register allocators to allocate predicate registers. Our improved transformation splits register allocation into two. First, the general-purpose registers are allocated as usual using a generic register allocator. Then, the main steps of the single-path transformation are performed while still using virtual predicate registers. Lastly, register allocation is rerun using the generic allocator to allocate the predicate registers. Our results show the improved single-path transformation increasing performance by up to 80 % and reducing code size by up to 43 % compared to the original transformation that uses a custom predicate allocator.
Original languageEnglish
Title of host publicationProceedings of the 2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC)
Number of pages12
PublisherIEEE
Publication date2024
ISBN (Print)979-8-3503-7129-1
ISBN (Electronic)979-8-3503-7128-4
DOIs
Publication statusPublished - 2024
Event2024 IEEE 27th International Symposium on Real-Time Distributed Computing - Tunis, Tunisia
Duration: 22 May 202425 May 2024

Conference

Conference2024 IEEE 27th International Symposium on Real-Time Distributed Computing
Country/TerritoryTunisia
CityTunis
Period22/05/202425/05/2024

Keywords

  • Real-time systems
  • Time-predictable computer architecture
  • Single-path
  • Constant execution time

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