Truncated multipliers through power-gating for degrading precision arithmetic

Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

When reducing the power dissipation of resource constrained electronic systems is a priority, some precision can be traded-off for lower power consumption. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we apply power-gating to multipliers to obtain a programmable truncated multiplier. The method consists in disabling the least-significant columns of the multiplier by power-gating logic in the partial products generation and accumulation array.
Original languageEnglish
Title of host publicationProceedings of 2013 Asilomar Conference on Signals, Systems and Computers
PublisherIEEE
Publication date2013
Pages2172-2176
ISBN (Print)978/1/4799/2390/8
DOIs
Publication statusPublished - 2013
Event2013 Asilomar Conference on Signals, Systems and Computers - Asilomar Conference Grounds, Pacific Grove, CA, United States
Duration: 3 Nov 20136 Nov 2013

Conference

Conference2013 Asilomar Conference on Signals, Systems and Computers
LocationAsilomar Conference Grounds
Country/TerritoryUnited States
CityPacific Grove, CA
Period03/11/201306/11/2013

Keywords

  • Bioengineering
  • Communication, Networking and Broadcast Technologies
  • Components, Circuits, Devices and Systems
  • Computing and Processing
  • Signal Processing and Analysis
  • Clocks
  • Delays
  • Digital signal processing
  • Finite impulse response filters
  • Layout
  • Logic gates
  • Power dissipation

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