Towards Time-predictable Data Caches for Chip-Multiprocessors

Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber

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Abstract

Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on the memory bandwidth and processor local caching is mandatory. However, data caches are known to be very hard to integrate into the worst-case execution time (WCET) analysis. We tackle this issue from the computer architecture side: provide a data cache organization that enables tight WCET analysis. Similar to the cache splitting between instruction and data, we argue to split the data cache for different data areas. In this paper we show cache simulation results for the split-cache organization, propose the modularization of the data cache analysis for the different data areas, and evaluate the implementation costs in a prototype chip-multiprocessor system.
Original languageEnglish
Title of host publicationProceedings of the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)
Publication date2009
Pages180-191
Chapter12
ISBN (Print)978-3-642-10264-6
ISBN (Electronic)978-3-642-10265-3
DOIs
Publication statusPublished - 2009
Externally publishedYes
EventSeventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009) - Newport Beach, (CA), United States
Duration: 16 Nov 200918 Nov 2009
Conference number: 7

Conference

ConferenceSeventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2009)
Number7
CountryUnited States
CityNewport Beach, (CA)
Period16/11/200918/11/2009
SeriesLecture Notes in Computer Science
Volume5860
ISSN0302-9743

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