Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Martin Schoeberl; Pascal Schleuniger; Wolfgang Puffitsch; Florian Brandner; Christian W. Probst; Sven Karlsson; Tommy Thorn

doi:10.4230/OASIcs.PPES.2011.11

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Martin Schoeberl
, Pascal Schleuniger
, Wolfgang Puffitsch
, Florian Brandner
, Christian W. Probst
, Sven Karlsson
, Tommy Thorn

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.

Original language	English
Title of host publication	OpenAccess Series in Informatics
Volume	18
Publisher	OASICS
Publication date	2011
Pages	11-21
ISBN (Print)	978-3-939897-28-6
DOIs	https://doi.org/10.4230/OASIcs.PPES.2011.11
Publication status	Published - 2011
Event	Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems - Grenoble, France Duration: 18 Mar 2011 → 18 Mar 2011

Workshop

Workshop	Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems
Country/Territory	France
City	Grenoble
Period	18/03/2011 → 18/03/2011

Keywords

WCET analysis
WCET-aware compilation
Time-predictable architecture

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10.4230/OASIcs.PPES.2011.11

Full textSubmitted manuscript, 174 KB
Full textFinal published version, 350 KB

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@inproceedings{dff7429db3254f09a2c897aad1f0e73c,

title = "Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach",

abstract = "Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.",

keywords = "WCET analysis, WCET-aware compilation, Time-predictable architecture",

author = "Martin Schoeberl and Pascal Schleuniger and Wolfgang Puffitsch and Florian Brandner and Probst, \{Christian W.\} and Sven Karlsson and Tommy Thorn",

year = "2011",

doi = "10.4230/OASIcs.PPES.2011.11",

language = "English",

isbn = "978-3-939897-28-6",

volume = "18",

pages = "11--21",

booktitle = "OpenAccess Series in Informatics",

publisher = "OASICS",

note = "Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems, PPES 2011 ; Conference date: 18-03-2011 Through 18-03-2011",

}

Schoeberl, M, Schleuniger, P, Puffitsch, W, Brandner, F, Probst, CW, Karlsson, S & Thorn, T 2011, Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach. in OpenAccess Series in Informatics. vol. 18, OASICS, pp. 11-21, Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Grenoble, France, 18/03/2011. https://doi.org/10.4230/OASIcs.PPES.2011.11

TY - GEN

T1 - Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

AU - Schoeberl, Martin

AU - Schleuniger, Pascal

AU - Puffitsch, Wolfgang

AU - Brandner, Florian

AU - Probst, Christian W.

AU - Karlsson, Sven

AU - Thorn, Tommy

PY - 2011

Y1 - 2011

N2 - Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.

AB - Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.

KW - WCET analysis

KW - WCET-aware compilation

KW - Time-predictable architecture

U2 - 10.4230/OASIcs.PPES.2011.11

DO - 10.4230/OASIcs.PPES.2011.11

M3 - Article in proceedings

SN - 978-3-939897-28-6

VL - 18

SP - 11

EP - 21

BT - OpenAccess Series in Informatics

PB - OASICS

T2 - Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems

Y2 - 18 March 2011 through 18 March 2011

ER -

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

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Keywords

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