Towards 100 Gbit/s Ethernet: Multicore-based Parallel Communication Protocol Design

Stavros Passas, Kostas Magoutis, Angelos Bilas

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires matching improvements in the system software stack. In this paper we address several sources of CPU and memory system overhead in the I/O path at line rates reaching 80 Gbits/s (bi-directional), using multiple 10 Gbit/s links per system node. Key contributions of our work are the design of a parallel high-performance communication protocol that uses context-independent page-remapping to (a) reduce packet processing overheads; (b) reduce thread management and synchronization overheads; and (c) address affinity issues in NUMA multicore CPUs. Our design result in the full 40 Gbits/s of available one-way Ethernet bandwidth and in 57.6 Gbits/s (72%) of the 80 Gbits/s maximum bidirectional throughput (limited only by the memory system), while leaving ample CPU cycles for application processing.
Original languageEnglish
Title of host publicationICS '09 Proceedings of the 23rd international conference on Supercomputing
PublisherACM
Publication date2009
Pages214-224
ISBN (Print)978-1-60558-498-0
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event23rd International Conference on Supercomputing - New York, NY, United States
Duration: 8 Jun 200912 Jun 2009
Conference number: 23
http://pcsostres.ac.upc.edu/ics-conference/archive/ics09/

Conference

Conference23rd International Conference on Supercomputing
Number23
CountryUnited States
CityNew York, NY
Period08/06/200912/06/2009
Internet address

Fingerprint

Dive into the research topics of 'Towards 100 Gbit/s Ethernet: Multicore-based Parallel Communication Protocol Design'. Together they form a unique fingerprint.

Cite this