Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso implementation shows that it is feasible to operate it at a frequency higher than 300 MHz in current state-of-the-art high end FPGAs.
|Title of host publication||Proceeding of third swedish workshop on multi-core computing - MCC'10|
|Publication status||Accepted/In press - 2010|
|Event||Swedish workshop on multi-core computing - Gothenburg, Sweden|
Duration: 1 Jan 2010 → …
Conference number: 3
|Conference||Swedish workshop on multi-core computing|
|Period||01/01/2010 → …|