Timing Analysis of Genetic Logic Circuits using D-VASim

A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to controlgene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electroniclogic circuits, timing and propagation delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing behavior of geneticlogic circuits but also to analyze the timing constraints of cascaded genetic logic circuits.