Time Sensitive Networking Ethernet:Architecture, Implementation and Applications

In this Industrial Ph.D. thesis we address the challenges of implementing Time Sensitive Networking (TSN) Ethernet switches in Field-Programmable Gate Array (FPGA) devices. TSN is a set of IEEE standards that extend Ethernet for real-time applications, which have to fulfill timing requirements. As such, TSN aims to replace proprietary technologies used in several real-time applications areas, from industrial automation to in-vehicle networking. FPGAs allow the (still-developing) TSN technology to benefit from the performance of Integrated Circuits (ICs). Various IC switch architectures have been proposed in the literature, each with its advantages and disadvantages. The Combined Input and Output Queued (CIOQ) crossbar architecture, which was chosen to be the focus of this thesis, is relatively simple to implement and scalable, while at the same time providing good performance. However, the forwarding behavior of the CIOQ crossbar differs from the abstract model assumed by the IEEE 802.1Q standard, where TSN features are described. Therefore, in this thesis we investigate, what are the impacts of this discrepancy. To that end, we provide scalability and performance evaluation of the FPGA implementation of the CIOQ crossbar switch. We additionally propose how to integrate the TSN feature modules with this CIOQ switch. Finally, we address the problem of traffic scheduling in TSN networks using Time Aware Shaper (TAS), where the characteristics of our CIOQ switch implementation had to be accounted for to create valid traffic schedules.