Virtual memory is an important feature of modern computer architectures. For hard real-time systems, memory protection is a particularly interesting feature of virtual memory. However, current memory management units are not designed for time-predictability and therefore cannot be used in such systems. This paper investigates the requirements on virtual memory from the perspective of hard real-time systems and presents the design of a time-predictable memory management unit. Our evaluation shows that the proposed design can be implemented efficiently. The design allows address translation and address range checking in constant time of two clock cycles on a cache miss. This constant time is in strong contrast to the possible cost of a miss in a translation look-aside buffer in traditional virtual memory organizations. Compared to a platform without a memory management unit, these two additional clock cycles per cache miss introduce only a small performance overhead.
|Title of host publication||Proceedings of the 19th International Symposium on Real-Time Distributed Computing (ISORC 2016)|
|Publication status||Published - 2016|
|Event||19th International Symposium on Real-Time Distributed Computing for Novel Applications and Systems - York, United Kingdom|
Duration: 17 May 2016 → 20 May 2016
Conference number: 19
|Conference||19th International Symposium on Real-Time Distributed Computing for Novel Applications and Systems|
|Period||17/05/2016 → 20/05/2016|