Time-predictable distributed shared on-chip memory

Morten B. Petersen, Anthon Vincent Riber, Simon T. Andersen, Martin Schoeberl

Research output: Contribution to journalJournal articleResearchpeer-review

Abstract

Multi-core processors for real-time systems need to have a time-predictable way of communicating. The use of a single, external shared memory is the standard for multi-core processor communication. However, this solution is hardly time-predictable. This paper presents a time-predictable solution for communication between cores, a distributed shared memory using a network-on-chip. The network-on-chip supports reading and writing data to and from distributed on-chip memory. This paper covers the implementation of time-predictable read requests on a network-on-chip. The network is implemented using static schedules, and time-division multiplexing, enabling predictions for worst-case execution time. The implementation attempts to keep buffering as low as possible to obtain a small footprint. The solution has been implemented and successfully synthesized with a multi-core system on an FPGA. Finally, we show resource and performance measurements.
Original languageEnglish
Article number102896
JournalMicroprocessors and Microsystems
Volume71
Number of pages9
ISSN0141-9331
DOIs
Publication statusPublished - 2019

Keywords

  • Network-on-chip
  • Distributed memory
  • Realtime systems

Cite this