Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

Mohammad Shajaan; John Aasted Sørensen

doi:10.1109/ICASSP.1996.550574

Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

Mohammad Shajaan, John Aasted Sørensen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing
Volume	Volume 6
Publisher	IEEE
Publication date	1996
Pages	3268-3271
ISBN (Print)	07-80-33192-3
DOIs	https://doi.org/10.1109/ICASSP.1996.550574
Publication status	Published - 1996
Event	1996 IEEE International Conference on Acoustics, Speech and Signal Processing - Atlanta, United States Duration: 7 May 1996 → 10 May 1996 Conference number: 21 http://www.eng.auburn.edu/~sjreeves/ICASSP/

Conference

Conference	1996 IEEE International Conference on Acoustics, Speech and Signal Processing
Number	21
Country/Territory	United States
City	Atlanta
Period	07/05/1996 → 10/05/1996
Internet address	http://www.eng.auburn.edu/~sjreeves/ICASSP/

Bibliographical note

Copyright 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Time-area efficient multiplier-free recursive filter architectures for FPGA implementation",

abstract = "Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach",

author = "Mohammad Shajaan and S{\o}rensen, {John Aasted}",

note = "Copyright 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 1996 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 1996 ; Conference date: 07-05-1996 Through 10-05-1996",

year = "1996",

doi = "10.1109/ICASSP.1996.550574",

language = "English",

isbn = "07-80-33192-3",

volume = "Volume 6",

pages = "3268--3271",

booktitle = "Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing",

publisher = "IEEE",

address = "United States",

url = "http://www.eng.auburn.edu/~sjreeves/ICASSP/",

}

Shajaan, M & Sørensen, JA 1996, Time-area efficient multiplier-free recursive filter architectures for FPGA implementation. in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing. vol. Volume 6, IEEE, pp. 3268-3271, 1996 IEEE International Conference on Acoustics, Speech and Signal Processing, Atlanta, Georgia, United States, 07/05/1996. https://doi.org/10.1109/ICASSP.1996.550574

Time-area efficient multiplier-free recursive filter architectures for FPGA implementation. / Shajaan, Mohammad; Sørensen, John Aasted.
Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing. Vol. Volume 6 IEEE, 1996. p. 3268-3271.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

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AU - Shajaan, Mohammad

AU - Sørensen, John Aasted

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PY - 1996

Y1 - 1996

N2 - Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach

AB - Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach

U2 - 10.1109/ICASSP.1996.550574

DO - 10.1109/ICASSP.1996.550574

M3 - Article in proceedings

SN - 07-80-33192-3

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SP - 3268

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BT - Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing

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T2 - 1996 IEEE International Conference on Acoustics, Speech and Signal Processing

Y2 - 7 May 1996 through 10 May 1996

ER -

Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

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