Time-area efficient multiplier-free filter architectures for FPGA implementation

Mohammad Shajaan, Karsten Nielsen, John Aasted Sørensen

    Research output: Contribution to journalConference articleResearchpeer-review

    349 Downloads (Pure)

    Abstract

    Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is 𝒪 (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach
    Original languageEnglish
    JournalI E E E International Conference on Acoustics, Speech and Signal Processing. Proceedings
    Volume5
    Pages (from-to)3251 - 3254
    ISSN1520-6149
    DOIs
    Publication statusPublished - 1995
    EventIEEE International Conference on Acoustics, Speech, and Signal Processing 1995 - Detroit, MI, United States
    Duration: 9 May 199512 May 1995

    Conference

    ConferenceIEEE International Conference on Acoustics, Speech, and Signal Processing 1995
    CountryUnited States
    CityDetroit, MI
    Period09/05/199512/05/1995

    Bibliographical note

    Copyright 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

    Fingerprint Dive into the research topics of 'Time-area efficient multiplier-free filter architectures for FPGA implementation'. Together they form a unique fingerprint.

    Cite this