Time-area efficient multiplier-free filter architectures for FPGA implementation

Mohammad Shajaan, Karsten Nielsen, John Aasted Sørensen

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    Abstract

    Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is 𝒪 (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach
    Original languageEnglish
    JournalI E E E International Conference on Acoustics, Speech and Signal Processing. Proceedings
    Volume5
    Pages (from-to)3251 - 3254
    ISSN1520-6149
    DOIs
    Publication statusPublished - 1995
    Event1995 IEEE International Conference on Acoustics, Speech, and Signal Processing - Detroit, United States
    Duration: 8 May 199512 May 1995
    Conference number: 20

    Conference

    Conference1995 IEEE International Conference on Acoustics, Speech, and Signal Processing
    Number20
    Country/TerritoryUnited States
    CityDetroit
    Period08/05/199512/05/1995

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