Time-area efficient multiplier-free filter architectures for FPGA implementation

Mohammad Shajaan; Karsten Nielsen; John Aasted Sørensen

doi:10.1109/ICASSP.1995.479578

Time-area efficient multiplier-free filter architectures for FPGA implementation

Mohammad Shajaan, Karsten Nielsen, John Aasted Sørensen

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Abstract

Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is &Oscr; (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach

Original language	English
Journal	I E E E International Conference on Acoustics, Speech and Signal Processing. Proceedings
Volume	5
Pages (from-to)	3251 - 3254
ISSN	1520-6149
DOIs	https://doi.org/10.1109/ICASSP.1995.479578
Publication status	Published - 1995
Event	1995 IEEE International Conference on Acoustics, Speech, and Signal Processing - Detroit, United States Duration: 8 May 1995 → 12 May 1995 Conference number: 20

Conference

Conference	1995 IEEE International Conference on Acoustics, Speech, and Signal Processing
Number	20
Country/Territory	United States
City	Detroit
Period	08/05/1995 → 12/05/1995

Bibliographical note

Copyright 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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@inproceedings{75f8aea0010d49d2b46dfd2d09b4a8ff,

title = "Time-area efficient multiplier-free filter architectures for FPGA implementation",

abstract = "Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is &Oscr; (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach",

author = "Mohammad Shajaan and Karsten Nielsen and S{\o}rensen, {John Aasted}",

note = "Copyright 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 1995 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95 ; Conference date: 08-05-1995 Through 12-05-1995",

year = "1995",

doi = "10.1109/ICASSP.1995.479578",

language = "English",

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issn = "1520-6149",

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T1 - Time-area efficient multiplier-free filter architectures for FPGA implementation

AU - Shajaan, Mohammad

AU - Nielsen, Karsten

AU - Sørensen, John Aasted

N1 - Conference code: 20

PY - 1995

Y1 - 1995

N2 - Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is &Oscr; (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach

AB - Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is &Oscr; (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach

U2 - 10.1109/ICASSP.1995.479578

DO - 10.1109/ICASSP.1995.479578

M3 - Conference article

SN - 1520-6149

VL - 5

SP - 3251

EP - 3254

JO - I E E E International Conference on Acoustics, Speech and Signal Processing. Proceedings

JF - I E E E International Conference on Acoustics, Speech and Signal Processing. Proceedings

T2 - 1995 IEEE International Conference on Acoustics, Speech, and Signal Processing

Y2 - 8 May 1995 through 12 May 1995

ER -

Time-area efficient multiplier-free filter architectures for FPGA implementation

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