Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

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    Abstract

    This paper describes a mathematical model of a balanced opto-electronic phase-locked loop (OPLL), which is required to be very fast for some network applications. OPLL is investigated in terms of clock pulse width, loop filter gain and residuals of the balancing DC level. Based on the guidelines from the theoretical evaluations, a very simple experimental demonstration including a single electroabsorption modulator as phase comparator is constructed.
    Original languageEnglish
    Title of host publicationTechnical Digest IEEE Laser and Elektro-Optics Society Annual Meeting
    PublisherIEEE
    Publication date2003
    PagesTuY5
    ISBN (Print)0-7803-7888-1
    DOIs
    Publication statusPublished - 2003
    Event16th Annual Meeting of the IEEE Lasers and Electro-Optics Society - Tuscon, United States
    Duration: 27 Oct 200328 Oct 2003
    Conference number: 16
    https://ieeexplore.ieee.org/xpl/conhome/8868/proceeding

    Conference

    Conference16th Annual Meeting of the IEEE Lasers and Electro-Optics Society
    Number16
    Country/TerritoryUnited States
    CityTuscon
    Period27/10/200328/10/2003
    Internet address

    Bibliographical note

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