Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

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Abstract

This paper describes a mathematical model of a balanced opto-electronic phase-locked loop (OPLL), which is required to be very fast for some network applications. OPLL is investigated in terms of clock pulse width, loop filter gain and residuals of the balancing DC level. Based on the guidelines from the theoretical evaluations, a very simple experimental demonstration including a single electroabsorption modulator as phase comparator is constructed.
Original languageEnglish
Title of host publicationTechnical Digest IEEE Laser and Elektro-Optics Society Annual Meeting
PublisherIEEE
Publication date2003
PagesTuY5
ISBN (Print)0-7803-7888-1
DOIs
Publication statusPublished - 2003
EventTechnical Digest IEEE Laser and Elektro-Optics Society Annual Meeting -
Duration: 1 Jan 2003 → …

Conference

ConferenceTechnical Digest IEEE Laser and Elektro-Optics Society Annual Meeting
Period01/01/2003 → …

Bibliographical note

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