Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

Darko Zibar; Leif Katsuo Oxenløwe; Anders Clausen; Jesper Mørk

doi:10.1109/LEOS.2003.1251827

Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

Darko Zibar, Leif Katsuo Oxenløwe, Anders Clausen, Jesper Mørk

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper describes a mathematical model of a balanced opto-electronic phase-locked loop (OPLL), which is required to be very fast for some network applications. OPLL is investigated in terms of clock pulse width, loop filter gain and residuals of the balancing DC level. Based on the guidelines from the theoretical evaluations, a very simple experimental demonstration including a single electroabsorption modulator as phase comparator is constructed.

Original language	English
Title of host publication	Technical Digest IEEE Laser and Elektro-Optics Society Annual Meeting
Publisher	IEEE
Publication date	2003
Pages	TuY5
ISBN (Print)	0-7803-7888-1
DOIs	https://doi.org/10.1109/LEOS.2003.1251827
Publication status	Published - 2003
Event	16th Annual Meeting of the IEEE Lasers and Electro-Optics Society - Tuscon, United States Duration: 27 Oct 2003 → 28 Oct 2003 Conference number: 16 https://ieeexplore.ieee.org/xpl/conhome/8868/proceeding

Conference

Conference	16th Annual Meeting of the IEEE Lasers and Electro-Optics Society
Number	16
Country/Territory	United States
City	Tuscon
Period	27/10/2003 → 28/10/2003
Internet address	https://ieeexplore.ieee.org/xpl/conhome/8868/proceeding

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s",

abstract = "This paper describes a mathematical model of a balanced opto-electronic phase-locked loop (OPLL), which is required to be very fast for some network applications. OPLL is investigated in terms of clock pulse width, loop filter gain and residuals of the balancing DC level. Based on the guidelines from the theoretical evaluations, a very simple experimental demonstration including a single electroabsorption modulator as phase comparator is constructed.",

author = "Darko Zibar and Oxenl{\o}we, {Leif Katsuo} and Anders Clausen and Jesper M{\o}rk",

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Zibar, D , Oxenløwe, LK , Clausen, A & Mørk, J 2003, Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s. in Technical Digest IEEE Laser and Elektro-Optics Society Annual Meeting. IEEE, pp. TuY5, 16th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Tuscon, Arizona, United States, 27/10/2003. https://doi.org/10.1109/LEOS.2003.1251827

Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s. / Zibar, Darko ; Oxenløwe, Leif Katsuo ; Clausen, Anders et al.

Technical Digest IEEE Laser and Elektro-Optics Society Annual Meeting. IEEE, 2003. p. TuY5.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AB - This paper describes a mathematical model of a balanced opto-electronic phase-locked loop (OPLL), which is required to be very fast for some network applications. OPLL is investigated in terms of clock pulse width, loop filter gain and residuals of the balancing DC level. Based on the guidelines from the theoretical evaluations, a very simple experimental demonstration including a single electroabsorption modulator as phase comparator is constructed.

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Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

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