Abstract
This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use
in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical
NoC topologies to be configured, thus providing both efficiency and flexibility. The article presents three
novel algorithms that synthesize an application-specific NoC topology, map it onto the physical ReNoC
architecture, and create deadlock-free, application-specific routing algorithms. We apply our algorithms
to a mixture of real and synthetic applications and target three different physical architectures. Compared
to a conventional NoC, ReNoC reduces power consumption by up to 58% on average.
Original language | English |
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Journal | A C M Transactions on Embedded Computing Systems |
Volume | 10 |
Issue number | 4 |
Pages (from-to) | 45:1-45:26 |
ISSN | 1539-9087 |
DOIs | |
Publication status | Published - 2011 |
Keywords
- Experimentation
- Algorithms
- System-on-chip
- Mapping
- Configuration
- Routing
- Performance
- Synthesis
- Network-on-chip