TY - RPRT
T1 - Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey
AU - Liu, Wei
PY - 2007
Y1 - 2007
N2 - This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated.
AB - This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated.
M3 - Report
BT - Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey
PB - Informatics and Mathematical Modelling, Technical University of Denmark, DTU
ER -