Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey

Wei Liu

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    This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated.
    Original languageEnglish
    PublisherInformatics and Mathematical Modelling, Technical University of Denmark, DTU
    Publication statusPublished - 2007

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