T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl; Sahar Abbaspourseyedi; Alexander Jordan; Evangelia Kasapaki; Wolfgang Puffitsch; Jens Sparsø; Benny Akesson; Neil Audsley; Jamie Garside; Raffaele Capasso; Alessandro Tocchi; Kees Goossens; Sven Goossens; Yonghui Li; Scott Hansen; Reinhold Heckmann; Stefan Hepp; Benedikt Huber; Jens Knoop; Daniel Prokesch; Peter Puschner; André Rocha; Cláudio Silva

doi:10.1016/j.sysarc.2015.04.002

T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl, Sahar Abbaspourseyedi, Alexander Jordan, Evangelia Kasapaki, Wolfgang Puffitsch, Jens Sparsø, Benny Akesson, Neil Audsley, Jamie Garside, Raffaele Capasso, Alessandro Tocchi, Kees Goossens, Sven Goossens, Yonghui Li, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Jens Knoop, Daniel ProkeschPeter Puschner, André Rocha, Cláudio Silva

Research output: Contribution to journal › Journal article › Research › peer-review

Abstract

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

Original language	English
Journal	Journal of Systems Architecture
Volume	61
Issue number	9
Pages (from-to)	449-471
ISSN	1383-7621
DOIs	https://doi.org/10.1016/j.sysarc.2015.04.002
Publication status	Published - 2015

Keywords

Real-time systems
Time-predictable computer architecture
Distributed computer systems
Embedded systems
Interactive computer systems
Memory architecture
Microprocessor chips
Network architecture
Network-on-chip
Program compilers
Real time systems
Signal processing
Static analysis
VLSI circuits
Collaborative research
Computation-intensive task
European Commission
Industrial use case
Multi-core processor
Multicore architectures
Signal processing applications
Worst-case execution time
Computer architecture

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10.1016/j.sysarc.2015.04.002

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Schoeberl, M., Abbaspourseyedi, S., Jordan, A., Kasapaki, E., Puffitsch, W., Sparsø, J., Akesson, B., Audsley, N., Garside, J., Capasso, R., Tocchi, A., Goossens, K., Goossens, S., Li, Y., Hansen, S., Heckmann, R., Hepp, S., Huber, B., Knoop, J., ... Silva, C. (2015). T-CREST: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture, 61(9), 449-471. https://doi.org/10.1016/j.sysarc.2015.04.002

@article{836481852a9f4f65b884e24ac1fe974f,

title = "T-CREST: Time-predictable multi-core architecture for embedded systems",

abstract = "Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.",

keywords = "Real-time systems, Time-predictable computer architecture, Distributed computer systems, Embedded systems, Interactive computer systems, Memory architecture, Microprocessor chips, Network architecture, Network-on-chip, Program compilers, Real time systems, Signal processing, Static analysis, VLSI circuits, Collaborative research, Computation-intensive task, European Commission, Industrial use case, Multi-core processor, Multicore architectures, Signal processing applications, Worst-case execution time, Computer architecture",

author = "Martin Schoeberl and Sahar Abbaspourseyedi and Alexander Jordan and Evangelia Kasapaki and Wolfgang Puffitsch and Jens Spars{\o} and Benny Akesson and Neil Audsley and Jamie Garside and Raffaele Capasso and Alessandro Tocchi and Kees Goossens and Sven Goossens and Yonghui Li and Scott Hansen and Reinhold Heckmann and Stefan Hepp and Benedikt Huber and Jens Knoop and Daniel Prokesch and Peter Puschner and Andr{\'e} Rocha and Cl{\'a}udio Silva",

year = "2015",

doi = "10.1016/j.sysarc.2015.04.002",

language = "English",

volume = "61",

pages = "449--471",

journal = "Journal of Systems Architecture",

issn = "1383-7621",

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Schoeberl, M, Abbaspourseyedi, S, Jordan, A, Kasapaki, E, Puffitsch, W, Sparsø, J, Akesson, B, Audsley, N, Garside, J, Capasso, R, Tocchi, A, Goossens, K, Goossens, S, Li, Y, Hansen, S, Heckmann, R, Hepp, S, Huber, B, Knoop, J, Prokesch, D, Puschner, P, Rocha, A & Silva, C 2015, 'T-CREST: Time-predictable multi-core architecture for embedded systems', Journal of Systems Architecture, vol. 61, no. 9, pp. 449-471. https://doi.org/10.1016/j.sysarc.2015.04.002

TY - JOUR

T1 - T-CREST: Time-predictable multi-core architecture for embedded systems

AU - Schoeberl, Martin

AU - Abbaspourseyedi, Sahar

AU - Jordan, Alexander

AU - Kasapaki, Evangelia

AU - Puffitsch, Wolfgang

AU - Sparsø, Jens

AU - Akesson, Benny

AU - Audsley, Neil

AU - Garside, Jamie

AU - Capasso, Raffaele

AU - Tocchi, Alessandro

AU - Goossens, Kees

AU - Goossens, Sven

AU - Li, Yonghui

AU - Hansen, Scott

AU - Heckmann, Reinhold

AU - Hepp, Stefan

AU - Huber, Benedikt

AU - Knoop, Jens

AU - Prokesch, Daniel

AU - Puschner, Peter

AU - Rocha, André

AU - Silva, Cláudio

PY - 2015

Y1 - 2015

N2 - Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

AB - Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

KW - Real-time systems

KW - Time-predictable computer architecture

KW - Distributed computer systems

KW - Embedded systems

KW - Interactive computer systems

KW - Memory architecture

KW - Microprocessor chips

KW - Network architecture

KW - Network-on-chip

KW - Program compilers

KW - Real time systems

KW - Signal processing

KW - Static analysis

KW - VLSI circuits

KW - Collaborative research

KW - Computation-intensive task

KW - European Commission

KW - Industrial use case

KW - Multi-core processor

KW - Multicore architectures

KW - Signal processing applications

KW - Worst-case execution time

KW - Computer architecture

U2 - 10.1016/j.sysarc.2015.04.002

DO - 10.1016/j.sysarc.2015.04.002

M3 - Journal article

SN - 1383-7621

VL - 61

SP - 449

EP - 471

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

IS - 9

ER -

T-CREST: Time-predictable multi-core architecture for embedded systems

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Keywords

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