T-CREST: Time-predictable multi-core architecture for embedded systems

Martin Schoeberl, Sahar Abbaspourseyedi, Alexander Jordan, Evangelia Kasapaki, Wolfgang Puffitsch, Jens Sparsø, Benny Akesson, Neil Audsley, Jamie Garside, Raffaele Capasso, Alessandro Tocchi, Kees Goossens, Sven Goossens, Yonghui Li, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Jens Knoop, Daniel ProkeschPeter Puschner, André Rocha, Cláudio Silva

Research output: Contribution to journalJournal articleResearchpeer-review

Abstract

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.
Original languageEnglish
JournalJournal of Systems Architecture
Volume61
Issue number9
Pages (from-to)449-471
ISSN1383-7621
DOIs
Publication statusPublished - 2015

Keywords

  • Real-time systems
  • Time-predictable computer architecture
  • Distributed computer systems
  • Embedded systems
  • Interactive computer systems
  • Memory architecture
  • Microprocessor chips
  • Network architecture
  • Network-on-chip
  • Program compilers
  • Real time systems
  • Signal processing
  • Static analysis
  • VLSI circuits
  • Collaborative research
  • Computation-intensive task
  • European Commission
  • Industrial use case
  • Multi-core processor
  • Multicore architectures
  • Signal processing applications
  • Worst-case execution time
  • Computer architecture

Cite this

Schoeberl, M., Abbaspourseyedi, S., Jordan, A., Kasapaki, E., Puffitsch, W., Sparsø, J., Akesson, B., Audsley, N., Garside, J., Capasso, R., Tocchi, A., Goossens, K., Goossens, S., Li, Y., Hansen, S., Heckmann, R., Hepp, S., Huber, B., Knoop, J., ... Silva, C. (2015). T-CREST: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture, 61(9), 449-471. https://doi.org/10.1016/j.sysarc.2015.04.002