Published results on Ge junctions are benchmarked systematically using RS–XJ plots. The electrical activation level required to meet the ITRS targets is calculated. Additionally, new results are presented on shallow furnace-annealed B junctions and shallow laser-annealed As junctions. Co-implanting B junctions with F is shown to degrade junction properties.
|Conference||Post-Si-CMOS electronic devices: the role of Ge and III-V materials|
|Period||01/01/2011 → …|
- Ultra Shallow Junction
- Sheet Resistance