System-Level Optimization of a DAC for Hearing-Aid Audio Class D Output Stage

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Abstract

This paper deals with system-level optimization of a digital-to-analog converter (DAC) for hearing-aid audio Class D output stage. We discuss the ΣΔ modulator system-level design parameters – the order, the oversampling ratio (OSR) and the number of bits in the quantizer. We show that combining a reduction of the OSR with an increase of the order results in considerable power savings while the audio quality is kept. For further savings in the ΣΔ modulator, overdesign and subsequent coarse coefficient quantization are used. A figure of merit (FOM) is introduced to confirm this optimization approach by comparing two ΣΔ modulator designs. The proposed optimization has impact on the whole hearing-aid audio back-end system including less hardware in the interpolation filter and half the switching rate in the digital-pulse-width-modulation (DPWM) block and Class D output stage
Original languageEnglish
Title of host publicationTechnological Innovation for the Internet of Things : 4th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems
Volume394
PublisherSpringer
Publication date2013
Pages647-654
ISBN (Print)978-3-642-37290-2
ISBN (Electronic)978-3-642-37291-9
DOIs
Publication statusPublished - 2013
Event4th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems - Costa de Caparica, Portugal
Duration: 15 Apr 201317 Apr 2013

Conference

Conference4th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems
CountryPortugal
CityCosta de Caparica
Period15/04/201317/04/2013
SeriesIFIP AICT - Advances in Information and Communication technology
Volume394
ISSN1868-4238

Keywords

  • Sigma-Delta Modulator
  • Digital-to-Analog Converter
  • Interpolation Filter
  • Class D
  • Hearing Aid
  • Low Voltage
  • Low Power

Cite this

Pracný, P., Jørgensen, I. H. H., & Bruun, E. (2013). System-Level Optimization of a DAC for Hearing-Aid Audio Class D Output Stage. In Technological Innovation for the Internet of Things : 4th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (Vol. 394, pp. 647-654 ). Springer. IFIP AICT - Advances in Information and Communication technology, Vol.. 394 https://doi.org/10.1007/978-3-642-37291-9_70