System Architecture of an Experimental Synthetic Aperture Real-Time Ultrasound System

Jørgen Arendt Jensen, Martin Hansen, Borislav Gueorguiev Tomov, Svetoslav Nikolov, Hans Holten-Lund

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Abstract

Synthetic Aperture (SA) ultrasound imaging has many advantages in terms of flexibility and accuracy. One of the major drawbacks is, however, that no system exists, which can implement SA imaging in real time due to the very high number of calculations amounting to roughly 1 billion complex focused samples per second per receive channel. Real time imaging is a key aspect in ultrasound, and to truly demonstrate the many advantages of SA imaging, a system usable in the clinic should be made. The paper describes a system capable of real time SA B-mode and vector flow imaging. The Synthetic Aperture Real-time Ultrasound System (SARUS) has been developed through the last 2 years and can perform real time SA imaging and storage of RF channel data for multiple seconds. SARUS consists of a 1024 channel analog front-end and 64 identical digital boards. Each has 16 transmit channels and 16 receive channels both with a sampling frequency of 70 MHz/12 bits for arbitrary waveform emission and reception. The board holds five Virtex 4FX100 FPGAs, where one houses a PowerPC CPU used for control. The remaining four are used for generation of transmit signals, receive storage and matched filter processing, and focusing and summing of data. Each FPGA can perform 80 billion multiplications/s and the full system can perform 25,600 billion multiplications/s. The FPGAs are connected through multiple 3.2 Gbit Rocket 10 links, which makes it possible to send more than 1.6 GBytes/s of data between the FPGAs and between boards. The system can concurrently sample in 1024 channels, thus, generating 140 GBytes/s of data, which also can be processed in real time or stored. The system is controlled over a 1 Gbit/s Ethernet link to each digital board that runs Linux. The control and processing are divided into functional units that are accessed through an IP numbering scheme in a hierarchical order. A single controlling mechanism can, thus, be used to access the whole system from any PC. It is also possible for the controlling PowerPCs to access all other boards, which enables advanced adaptive imaging. The software is written in C++ and runs under Matlab for high level access to the system in a command structure similar to the Field 11 simulation program. This makes it possible for the user to specify imaging in very few lines of code and the set-up is fast due to the employment of the 64 PowerPCs in parallel. Focusing is done using a parametric beam former. Code synthesized for a Xilinx V4FX100 speed grade 11 FPGA can operate at a maximum clock frequency of 167.8 MHz producing 1 billion I and Q samples/second sufficient for real time SA imaging. The system is currently in production, and all boards have been laid out. VHDL and C++ code for the control has been written and the code for real time beamformation has been made and has obtained a sufficient performance for real-time imaging.
Original languageEnglish
Title of host publicationIEEE Ultrasonics Symposium
PublisherIEEE
Publication date2007
Pages636-640
ISBN (Print)978-1-4244-1383-6
DOIs
Publication statusPublished - 2007
Event2007 IEEE International Ultrasonics Symposium - New Yortk, United States
Duration: 28 Oct 200731 Oct 2007
Conference number: 12B-3
http://ewh.ieee.org/conf/ius_2007/

Conference

Conference2007 IEEE International Ultrasonics Symposium
Number12B-3
CountryUnited States
CityNew Yortk
Period28/10/200731/10/2007
OtherValidation of Transverse Oscillation Vector Velocity Estimation In-Vivo
Internet address

Bibliographical note

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