Synthetic aperture radar, SAR, is a high resolution imaging radar. The direct back-projection algorithm allows for a precise SAR output image reconstruction and can compensate for deviations in the flight track of airborne radars. Often graphic processing units, GPUs are used for data processing as the back-projection algorithm is computationally expensive and highly parallel. However, GPUs may not be an appropriate solution for applications with strictly constrained space and power requirements. In this paper, we describe how we map a SAR direct back-projection application to a multi-core system on an FPGA. The fabric consisting of 64 processor cores and 2D mesh interconnect utilizes 60% of the hardware resources of a Xilinx Virtex-7 device with 550 thousand logic cells and consumes about 10 watt. We apply software pipelining to hide memory latency and reduce the hardware footprint by 14%. We show that the system provides real-time processing of a SAR application that maps a 3000m wide area with a resolution of 2x2 meters.
|Title of host publication||Architecture of Computing Systems – ARCS 2013 : 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings|
|Publication status||Published - 2013|
|Event||26th International Conference on Architecture of Computing Systems (ARCS 2013) - Prague, Czech Republic|
Duration: 19 Feb 2013 → 22 Feb 2013
|Conference||26th International Conference on Architecture of Computing Systems (ARCS 2013)|
|Period||19/02/2013 → 22/02/2013|
|Series||Lecture Notes in Computer Science|