We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.
|Title of host publication||International Workshop on Electronic Design, Test & Applications|
|Publication status||Published - 2006|
|Event||Third IEEE International Workshop on Electronic Design, Test and Applications - Kuala Lumpur, Malaysia|
Duration: 17 Jan 2006 → 19 Jan 2006
Conference number: 3
|Workshop||Third IEEE International Workshop on Electronic Design, Test and Applications|
|Period||17/01/2006 → 19/01/2006|