This work addresses the issue of design optimization for fault- tolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpointing with rollback recovery and active replication. Fault tolerant schedules are generated based on a conditional process graph representation. The formulated system synthesis approaches decide the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors, such that multiple transient faults are tolerated, transparency requirements are considered, and the timing constraints of the application are satisfied.
|Title of host publication||Design, Automation, and Test in Europe Conference|
|Publication status||Published - 2008|
|Event||2008 Design, Automation and Test in Europe - Munich, Germany|
Duration: 10 Mar 2008 → 14 Mar 2008
|Conference||2008 Design, Automation and Test in Europe|
|Period||10/03/2008 → 14/03/2008|