Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

Christoph Müller; Evangelia Kasapaki; Rasmus Bo Sørensen; Jens Sparsø

doi:10.1109/NORCHIP.2014.7004742

Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

Christoph Müller, Evangelia Kasapaki, Rasmus Bo Sørensen, Jens Sparsø

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

1 Downloads (Pure)

Abstract

Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented elsewhere.

Original language	English
Title of host publication	Proceedings of the 32nd NORCHIP Conference 2014
Number of pages	6
Publisher	IEEE
Publication date	2014
Pages	1-6
ISBN (Print)	978-1-4799-6890-9
DOIs	https://doi.org/10.1109/NORCHIP.2014.7004742
Publication status	Published - 2014
Event	2014 IEEE 32nd NORCHIP Conference - Tampere, Finland Duration: 27 Oct 2014 → 28 Oct 2014 Conference number: 32 https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding

Conference

Conference	2014 IEEE 32nd NORCHIP Conference
Number	32
Country/Territory	Finland
City	Tampere
Period	27/10/2014 → 28/10/2014
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding

Keywords

Multiprocessor interconnection networks
Asynchronous design
Asynchronous implementation

Access to Document

10.1109/NORCHIP.2014.7004742

OpenUrl availability

Full text

Cite this

@inproceedings{5d8d0a1e0c7a49fc8456e1481e2822ef,

title = "Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools",

abstract = "Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented elsewhere.",

keywords = "Multiprocessor interconnection networks, Asynchronous design, Asynchronous implementation",

author = "Christoph M{\"u}ller and Evangelia Kasapaki and S{\o}rensen, {Rasmus Bo} and Jens Spars{\o}",

year = "2014",

doi = "10.1109/NORCHIP.2014.7004742",

language = "English",

isbn = "978-1-4799-6890-9",

pages = "1--6",

booktitle = "Proceedings of the 32nd NORCHIP Conference 2014",

publisher = "IEEE",

address = "United States",

note = "2014 IEEE 32nd NORCHIP Conference, NORCHIP 2014 ; Conference date: 27-10-2014 Through 28-10-2014",

url = "https://ieeexplore.ieee.org/xpl/conhome/6962987/proceeding",

}

TY - GEN

T1 - Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

AU - Müller, Christoph

AU - Kasapaki, Evangelia

AU - Sørensen, Rasmus Bo

AU - Sparsø, Jens

N1 - Conference code: 32

PY - 2014

Y1 - 2014

N2 - Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented elsewhere.

AB - Asynchronous circuit design is well understood but design tools supporting asynchronous design are largely lacking, and designers are limited to using conventional EDA-tools. These tools have a built-in synchronous mind-set and this complicates their use for asynchronous implementation. One example is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented elsewhere.

KW - Multiprocessor interconnection networks

KW - Asynchronous design

KW - Asynchronous implementation

U2 - 10.1109/NORCHIP.2014.7004742

DO - 10.1109/NORCHIP.2014.7004742

M3 - Article in proceedings

SN - 978-1-4799-6890-9

SP - 1

EP - 6

BT - Proceedings of the 32nd NORCHIP Conference 2014

PB - IEEE

T2 - 2014 IEEE 32nd NORCHIP Conference

Y2 - 27 October 2014 through 28 October 2014

ER -

Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

Abstract

Conference

Keywords

Access to Document

OpenUrl availability

Fingerprint

Cite this