To meet the ever increasing demands for small lightweight consumer chargers, solutions to achieve higher switching frequencies are required. In this paper we show that it is essential to implement a synchronous rectifier for furthering advancements in power density. The shortcomings of diodes are illustrated, their main disadvantage being their large power losses ranging from 6002500. We propose a synchronous rectifier based on a Phase Locked Loop (PLL). An application specific integrated circuit containing a PLL designed for a synchronous rectifier was taped out in a 0.18 CMOS process. The PLL has an area of 0.05, and the total area containing two level shifters and gate drivers is 0.21. Two main issues with the PLL based synchronous rectifier are identified, the locking time and the RMS jitter. The designed PLL achieves a sufficient phase noise performance, of 8 RMS jitter, which from simulations have been shown to have a minimal impact on the efficiency. The locking time of the PLL is measured to 8. The resulting synchronous rectifier prototype showed a possible efficiency improvement of up to 1.8%, removing 1/8 of the total power loss, compared to a purely passive rectifier.
|Journal||IEEE Journal of Emerging and Selected Topics in Power Electronics|
|Pages (from-to)||2227 - 2237|
|Publication status||Published - 2020|
Bibliographical noteSpecial Issue on Topologies, Modeling Methodologies and Control Techniques for High-Frequency Power