Abstract
A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.
Original language | English |
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Title of host publication | 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017) |
Number of pages | 4 |
Publisher | IEEE |
Publication date | 2017 |
ISBN (Electronic) | 978-1-5090-5025-3 |
DOIs | |
Publication status | Published - 2017 |
Event | ESSCIRC 43rd European Solid-State Circuits Conference - Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017 Conference number: 43 https://www.esscirc-essderc2017.org |
Conference
Conference | ESSCIRC 43rd European Solid-State Circuits Conference |
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Number | 43 |
Country/Territory | Belgium |
City | Leuven |
Period | 11/09/2017 → 14/09/2017 |
Internet address |