Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control

Dennis Øland Larsen; Martin Vinter; Ivan Harald Holger Jørgensen

doi:10.1109/ESSCIRC.2017.8094581

Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control

Dennis Øland Larsen, Martin Vinter, Ivan Harald Holger Jørgensen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

397 Downloads (Pure)

Abstract

A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.

Original language	English
Title of host publication	43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017)
Number of pages	4
Publisher	IEEE
Publication date	2017
ISBN (Electronic)	978-1-5090-5025-3
DOIs	https://doi.org/10.1109/ESSCIRC.2017.8094581
Publication status	Published - 2017
Event	ESSCIRC 43rd European Solid-State Circuits Conference - Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017 Conference number: 43 https://www.esscirc-essderc2017.org

Conference

Conference	ESSCIRC 43rd European Solid-State Circuits Conference
Number	43
Country	Belgium
City	Leuven
Period	11/09/2017 → 14/09/2017
Internet address	https://www.esscirc-essderc2017.org

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10.1109/ESSCIRC.2017.8094581

Larsen dennis switched capacitor dcdc esscirc17 v3Accepted author manuscript, 1.64 MB

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@inproceedings{9b878a2c18e04d57b53a36ed0a23179f,

title = "Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control",

abstract = "A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.",

author = "Larsen, {Dennis {\O}land} and Martin Vinter and J{\o}rgensen, {Ivan Harald Holger}",

year = "2017",

doi = "10.1109/ESSCIRC.2017.8094581",

language = "English",

booktitle = "43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017)",

publisher = "IEEE",

address = "United States",

note = "ESSCIRC 43rd European Solid-State Circuits Conference, ESSCIRC 2017 ; Conference date: 11-09-2017 Through 14-09-2017",

url = "https://www.esscirc-essderc2017.org",

}

Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control. / Larsen, Dennis Øland; Vinter, Martin; Jørgensen, Ivan Harald Holger.

43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017). IEEE, 2017.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - Switched capacitor DC-DC converter with switch conductance modulation and Pesudo-fixed frequency control

AU - Larsen, Dennis Øland

AU - Vinter, Martin

AU - Jørgensen, Ivan Harald Holger

N1 - Conference code: 43

PY - 2017

Y1 - 2017

N2 - A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.

AB - A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller is implemented in 180 CMOS with a 1/3 series-parallel output stage designed for 3.6–4.2 V input, 1.2 V output, and 1–40 mA load current. The proposed controller is compared with a co-integrated pulse skipping controller and yields a 84.8% reduction in worst-case low-load output ripple voltage and a 1.5% increase in peak efficiency reaching 92.5%, while also providing a predictable spectrum of the switching noise, reducing the risk of interfering with other sensitive circuits.

U2 - 10.1109/ESSCIRC.2017.8094581

DO - 10.1109/ESSCIRC.2017.8094581

M3 - Article in proceedings

BT - 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017)

PB - IEEE

T2 - ESSCIRC 43rd European Solid-State Circuits Conference

Y2 - 11 September 2017 through 14 September 2017

ER -