Utilizing a stack cache in a real-time system can aid predictability by avoiding interference that heap memory traffic causes on the data cache. While loads and stores are guaranteed cache hits, explicit operations are responsible for managing the stack cache. The behavior of these operations can be analyzed statically. We present algorithms that derive worst-case bounds on the latency-inducing operations of the stack cache. Their results can be used by a static WCET tool. By breaking the analysis down into subproblems that solve intra-procedural data-flow analysis and path searches on the call-graph, the worst-case bounds can be efficiently yet precisely determined. Our evaluation using the MiBench benchmark suite shows that only 37% and 21% of potential stack cache operations actually store to and load from memory, respectively. Analysis times are modest, on average running between 0.46s and 1.30s per benchmark, depending on the size of the stack cache.
|Title of host publication||Proceedings of the 21st International conference on Real-Time Networks and Systems|
|Publisher||Association for Computing Machinery|
|Publication status||Published - 2013|
|Event||21st International conference on Real-Time Networks and Systems (RTNS 2013) - Sophia Antipolis, France|
Duration: 16 Oct 2013 → 18 Oct 2013
|Conference||21st International conference on Real-Time Networks and Systems (RTNS 2013)|
|Period||16/10/2013 → 18/10/2013|