Stack Caching Using Split Data Caches

Carsten Nielsen, Martin Schoeberl

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

In most embedded and general purpose architectures, stack data and non-stack data is cached together, meaning that writing to or loading from the stack may expel non-stack data from the data cache. Manipulation of the stack has a different memory access pattern than that of non-stack data, showing higher temporal and spatial locality. We propose caching stack and non-stack data separately and develop four different stack caches that allow this separation without requiring compiler support. These are the simple, window, and prefilling with and without tag stack caches. The performance of the stack cache architectures was evaluated using the Simple Scalar toolset where the window and prefilling stack cache without tag resulted in an execution speedup of up to 3.5% for the MiBench benchmarks, executed on an out-of-order processor with the ARM instruction set.
Original languageEnglish
Title of host publicationProceedings of the 18th International Symposium on Real-Time Distributed Computing Workshops (ISORCW 2015)
PublisherIEEE
Publication date2015
Pages66-73
ISBN (Print)978-1-4799-7709-6
DOIs
Publication statusPublished - 2015
Event18th IEEE International Symposium on Real-time Computing - Auckland, New Zealand
Duration: 13 Apr 201517 Apr 2015
Conference number: 18
http://www.isorc2015.org/

Conference

Conference18th IEEE International Symposium on Real-time Computing
Number18
CountryNew Zealand
CityAuckland
Period13/04/201517/04/2015
Internet address

Keywords

  • Cache Memory
  • Microprocessors
  • Stack Caching

Cite this

Nielsen, C., & Schoeberl, M. (2015). Stack Caching Using Split Data Caches. In Proceedings of the 18th International Symposium on Real-Time Distributed Computing Workshops (ISORCW 2015) (pp. 66-73). IEEE. https://doi.org/10.1109/ISORCW.2015.59