Software-Defined GPS Receiver Implemented on the Parallella-16 Board

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Abstract

This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).
Original languageEnglish
Title of host publicationProceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015)
PublisherThe Institute of Navigation
Publication date2015
Pages3171 - 3177
Publication statusPublished - 2015
Event 28th International Technical Meeting of The Satellite Division of the Institute of Navigation - Tampa Convention Center, Tampa, United States
Duration: 14 Sep 201518 Sep 2015
https://www.ion.org/gnss/past-meetings.cfm

Conference

Conference 28th International Technical Meeting of The Satellite Division of the Institute of Navigation
LocationTampa Convention Center
CountryUnited States
CityTampa
Period14/09/201518/09/2015
Internet address

Cite this

Olesen, D. M., Jakobsen, J., & Knudsen, P. (2015). Software-Defined GPS Receiver Implemented on the Parallella-16 Board. In Proceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015) (pp. 3171 - 3177 ). The Institute of Navigation.
Olesen, Daniel Madelung ; Jakobsen, Jakob ; Knudsen, Per. / Software-Defined GPS Receiver Implemented on the Parallella-16 Board. Proceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015). The Institute of Navigation, 2015. pp. 3171 - 3177
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abstract = "This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).",
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Olesen, DM, Jakobsen, J & Knudsen, P 2015, Software-Defined GPS Receiver Implemented on the Parallella-16 Board. in Proceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015). The Institute of Navigation, pp. 3171 - 3177 , 28th International Technical Meeting of The Satellite Division of the Institute of Navigation, Tampa, United States, 14/09/2015.

Software-Defined GPS Receiver Implemented on the Parallella-16 Board. / Olesen, Daniel Madelung; Jakobsen, Jakob; Knudsen, Per.

Proceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015). The Institute of Navigation, 2015. p. 3171 - 3177 .

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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AB - This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).

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Olesen DM, Jakobsen J, Knudsen P. Software-Defined GPS Receiver Implemented on the Parallella-16 Board. In Proceedings of the 28th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2015). The Institute of Navigation. 2015. p. 3171 - 3177