Selective Epitaxy of III-V/Si Nanostructures for Extreme Dielectric Confinement

The integration of III-V semiconductors on silicon is a promising route towards scalable, high performance photonic platforms, yet challenges such as lattice mismatch and thermal expansion differences hinder monolithic light source realization. This thesis addresses these issues using selective area epitaxy (SAE) to enable defect-minimized growth of InP/InAsP heterostructures on silicon and tunnel epitaxy to enable subwavelength growth of InP on silicon-on-insulator substrates. We investigate epitaxial growth mechanisms, highlighting the roles growth temperature, V/III ratio and role of template geometry in achieving selective, uniform nucleation with high crystal quality. Building on this, epitaxially grown InAsP nano-emitters are integrated with nanobeam photonic crystal cavities, achieving strong light matter coupling and ten-fold photoluminescence enhancement at room temperature. Optical studies confirm cavity-enhanced spontaneous emission, enabling operation of nanoLED. Collectively, this work demonstrates a complete pathway from nanoscale growth to device level integration, paving the way for scalable III-V/Si optoelectronic and quantum photonic platform.