Activities per year
This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.
|Title of host publication||Proceedings of OPNETWORK 2011|
|Publication status||Published - 2011|
|Event||OPNETWORK 2011 - Washington DC, United States|
Duration: 29 Aug 2011 → 1 Sep 2011
|Period||29/08/2011 → 01/09/2011|