SDRAM-based packet buffer model for high speed switches

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    This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.
    Original languageEnglish
    Title of host publicationProceedings of OPNETWORK 2011
    Publication date2011
    Publication statusPublished - 2011
    EventOPNETWORK 2011 - Washington DC, United States
    Duration: 29 Aug 20111 Sept 2011


    ConferenceOPNETWORK 2011
    Country/TerritoryUnited States
    CityWashington DC
    Internet address


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    • OPNETWORK 2011

      Hao Yu (Participant)

      27 Aug 20112 Sept 2011

      Activity: Attending an eventParticipating in or organising workshops, courses, seminars etc.

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