SDRAM-based packet buffer model for high speed switches

Anders Rasmussen; Sarah Renée Ruepp; Michael Stübert Berger; Henrik Wessing; Hao Yu

SDRAM-based packet buffer model for high speed switches

Anders Rasmussen, Sarah Renée Ruepp, Michael Stübert Berger, Henrik Wessing, Hao Yu

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.

Original language	English
Title of host publication	Proceedings of OPNETWORK 2011
Publication date	2011
Publication status	Published - 2011
Event	OPNETWORK 2011 - Washington DC, United States Duration: 29 Aug 2011 → 1 Sept 2011 http://www.opnet.com/opnetwork2011/

Conference

Conference	OPNETWORK 2011
Country/Territory	United States
City	Washington DC
Period	29/08/2011 → 01/09/2011
Internet address	http://www.opnet.com/opnetwork2011/

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OPNETWORK 2011
Yu, H. (Participant)
27 Aug 2011 → 2 Sept 2011
Activity: Attending an event › Participating in or organising workshops, courses, seminars etc.

Cite this

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title = "SDRAM-based packet buffer model for high speed switches",

abstract = "This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.",

author = "Anders Rasmussen and Ruepp, {Sarah Ren{\'e}e} and Berger, {Michael St{\"u}bert} and Henrik Wessing and Hao Yu",

year = "2011",

language = "English",

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note = "OPNETWORK 2011 ; Conference date: 29-08-2011 Through 01-09-2011",

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T1 - SDRAM-based packet buffer model for high speed switches

AU - Rasmussen, Anders

AU - Ruepp, Sarah Renée

AU - Berger, Michael Stübert

AU - Wessing, Henrik

AU - Yu, Hao

PY - 2011

Y1 - 2011

N2 - This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.

AB - This article investigates the how the performance of SDRAM based packet buffering systems for high performance switches can be simulated using OPNET. In order to include the access pattern dependent performance of SDRAM modules in simulations, a custom SDRAM model is implemented in OPNET Modeller based on the specifications of a real-life DDR3-SDRAM chip. Based on this model the performance of different schemes for optimizing the performance of such a packet buffer can be evaluated. The purpose of this study is to find efficient schemes for memory mapping of the packet queues and I/O traffic shaping to provide the best performance in terms of latency and throughput.

M3 - Article in proceedings

BT - Proceedings of OPNETWORK 2011

T2 - OPNETWORK 2011

Y2 - 29 August 2011 through 1 September 2011

ER -

SDRAM-based packet buffer model for high speed switches

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OPNETWORK 2011

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