Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

Petru Eles; Krzysztof Kuchcinski; Zebo Peng; Paul Pop; Alex Doboli

doi:10.1109/DATE.1998.655847

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Paul Pop, Alex Doboli

Linköping University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Original language	English
Title of host publication	Proceedings of the conference on Design, automation and test in Europe : The Most Influential Papers of 10 Years DATE
Publisher	Springer
Publication date	1998
Pages	132-138
ISBN (Print)	978-1-4020-6487-6, 0-8186-8359-7
DOIs	https://doi.org/10.1109/DATE.1998.655847
Publication status	Published - 1998
Event	1998 Design, Automation and Test in Europe - Paris, France Duration: 23 Feb 1998 → 26 Feb 1998 http://www.informatik.uni-trier.de/~ley/db/conf/date/date1998.html

Conference

Conference	1998 Design, Automation and Test in Europe
Country/Territory	France
City	Paris
Period	23/02/1998 → 26/02/1998
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/date/date1998.html

Bibliographical note

Copyright note for papers published by the IEEE Computer Society: Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.

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title = "Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems",

abstract = "We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.",

author = "Petru Eles and Krzysztof Kuchcinski and Zebo Peng and Paul Pop and Alex Doboli",

note = "Copyright note for papers published by the IEEE Computer Society: Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.; 1998 Design, Automation and Test in Europe, DATE '98 ; Conference date: 23-02-1998 Through 26-02-1998",

year = "1998",

doi = "10.1109/DATE.1998.655847",

language = "English",

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Eles, P, Kuchcinski, K, Peng, Z, Pop, P & Doboli, A 1998, Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. in Proceedings of the conference on Design, automation and test in Europe: The Most Influential Papers of 10 Years DATE. Springer, pp. 132-138, 1998 Design, Automation and Test in Europe, Paris, France, 23/02/1998. https://doi.org/10.1109/DATE.1998.655847

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. / Eles, Petru; Kuchcinski, Krzysztof; Peng, Zebo et al.
Proceedings of the conference on Design, automation and test in Europe: The Most Influential Papers of 10 Years DATE. Springer, 1998. p. 132-138.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AU - Eles, Petru

AU - Kuchcinski, Krzysztof

AU - Peng, Zebo

AU - Pop, Paul

AU - Doboli, Alex

N1 - Copyright note for papers published by the IEEE Computer Society: Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.

PY - 1998

Y1 - 1998

N2 - We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

AB - We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

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DO - 10.1109/DATE.1998.655847

M3 - Article in proceedings

SN - 978-1-4020-6487-6

SN - 0-8186-8359-7

SP - 132

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BT - Proceedings of the conference on Design, automation and test in Europe

PB - Springer

T2 - 1998 Design, Automation and Test in Europe

Y2 - 23 February 1998 through 26 February 1998

ER -

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

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