We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
|Title of host publication||Proceedings of the conference on Design, automation and test in Europe : The Most Influential Papers of 10 Years DATE|
|ISBN (Print)||978-1-4020-6487-6, 0-8186-8359-7|
|Publication status||Published - 1998|
|Event||1998 Design, Automation and Test in Europe - Paris, France|
Duration: 23 Feb 1998 → 26 Feb 1998
|Conference||1998 Design, Automation and Test in Europe|
|Period||23/02/1998 → 26/02/1998|