Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Paul Pop, Alex Doboli

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    We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.
    Original languageEnglish
    Title of host publicationProceedings of the conference on Design, automation and test in Europe : The Most Influential Papers of 10 Years DATE
    Publication date1998
    ISBN (Print)978-1-4020-6487-6, 0-8186-8359-7
    Publication statusPublished - 1998
    Event1998 Design, Automation and Test in Europe - Paris, France
    Duration: 23 Feb 199826 Feb 1998


    Conference1998 Design, Automation and Test in Europe
    Internet address

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