In this paper we present an algorithm for system level hardware/software partitioning of heterogeneous embedded systems. The system is represented as an abstract graph which captures both data-flow and the flow of control. Given an architecture consisting of several processors, ASICs and shared busses, our partitioning algorithm finds the partitioning with the smallest hardware cost and is able to predict and guarantee the performance of the system in terms of worst case delay.
|Title of host publication||Swedish Workshop on Computer Systems Architecture|
|Publication status||Published - 1998|
|Event||Swedish Workshop on Computer Systems Architecture - |
Duration: 1 Jan 1998 → …
|Conference||Swedish Workshop on Computer Systems Architecture|
|Period||01/01/1998 → …|