Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Research output: Contribution to journalConference article – Annual report year: 2003Researchpeer-review

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Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. / Pop, Paul; Eles, Petru; Peng, Zebo.

In: IEE Proceedings - Computers and digital Techniques, Vol. 150, No. 5, 2003, p. 303-312.

Research output: Contribution to journalConference article – Annual report year: 2003Researchpeer-review

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@inproceedings{fda639cdd809482ab3298d759b158c6c,
title = "Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems",
abstract = "An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.",
author = "Paul Pop and Petru Eles and Zebo Peng",
year = "2003",
doi = "10.1049/ip-cdt:20030829",
language = "English",
volume = "150",
pages = "303--312",
journal = "IEE Proceedings - Computers and digital Techniques",
issn = "1350-2387",
publisher = "Institution of Electrical Engineers (IEE)",
number = "5",

}

RIS

TY - GEN

T1 - Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

AU - Pop, Paul

AU - Eles, Petru

AU - Peng, Zebo

PY - 2003

Y1 - 2003

N2 - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

AB - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

U2 - 10.1049/ip-cdt:20030829

DO - 10.1049/ip-cdt:20030829

M3 - Conference article

VL - 150

SP - 303

EP - 312

JO - IEE Proceedings - Computers and digital Techniques

JF - IEE Proceedings - Computers and digital Techniques

SN - 1350-2387

IS - 5

ER -