Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

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An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.
Original languageEnglish
JournalIEE Proceedings - Computers and digital Techniques
Issue number5
Pages (from-to)303-312
Publication statusPublished - 2003
Event2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany
Duration: 3 Mar 20037 Mar 2003


Conference2003 Design, Automation and Test in Europe Conference and Exposition
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CitationsWeb of Science® Times Cited: No match on DOI

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