Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Paul Pop; Petru Eles; Zebo Peng

doi:10.1049/ip-cdt:20030829

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Paul Pop
, Petru Eles
, Zebo Peng

Linköping University

Research output: Contribution to journal › Conference article › Research › peer-review

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Abstract

An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

Original language	English
Journal	IEE Proceedings - Computers and digital Techniques
Volume	150
Issue number	5
Pages (from-to)	303-312
ISSN	1350-2387
DOIs	https://doi.org/10.1049/ip-cdt:20030829
Publication status	Published - 2003
Event	2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany Duration: 3 Mar 2003 → 7 Mar 2003 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

Conference

Conference	2003 Design, Automation and Test in Europe Conference and Exposition
Country/Territory	Germany
City	Munich
Period	03/03/2003 → 07/03/2003
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

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title = "Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems",

abstract = "An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.",

author = "Paul Pop and Petru Eles and Zebo Peng",

year = "2003",

doi = "10.1049/ip-cdt:20030829",

language = "English",

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note = "2003 Design, Automation and Test in Europe Conference and Exposition, DATE 2003 ; Conference date: 03-03-2003 Through 07-03-2003",

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AU - Eles, Petru

AU - Peng, Zebo

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N2 - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

AB - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

U2 - 10.1049/ip-cdt:20030829

DO - 10.1049/ip-cdt:20030829

M3 - Conference article

SN - 1350-2387

VL - 150

SP - 303

EP - 312

JO - IEE Proceedings - Computers and digital Techniques

JF - IEE Proceedings - Computers and digital Techniques

IS - 5

T2 - 2003 Design, Automation and Test in Europe Conference and Exposition

Y2 - 3 March 2003 through 7 March 2003

ER -

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Abstract

Conference

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