Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Paul Pop, Petru Eles, Zebo Peng

    Research output: Contribution to journalConference articleResearchpeer-review

    235 Downloads (Pure)

    Abstract

    An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.
    Original languageEnglish
    JournalIEE Proceedings - Computers and digital Techniques
    Volume150
    Issue number5
    Pages (from-to)303-312
    ISSN1350-2387
    DOIs
    Publication statusPublished - 2003
    Event2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany
    Duration: 3 Mar 20037 Mar 2003
    http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

    Conference

    Conference2003 Design, Automation and Test in Europe Conference and Exposition
    CountryGermany
    CityMunich
    Period03/03/200307/03/2003
    Internet address

    Cite this

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    title = "Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems",
    abstract = "An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.",
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    year = "2003",
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    language = "English",
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    pages = "303--312",
    journal = "IEE Proceedings - Computers and digital Techniques",
    issn = "1350-2387",
    publisher = "Institution of Electrical Engineers (IEE)",
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    Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. / Pop, Paul; Eles, Petru; Peng, Zebo.

    In: IEE Proceedings - Computers and digital Techniques, Vol. 150, No. 5, 2003, p. 303-312.

    Research output: Contribution to journalConference articleResearchpeer-review

    TY - GEN

    T1 - Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

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    AU - Eles, Petru

    AU - Peng, Zebo

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    N2 - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

    AB - An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.

    U2 - 10.1049/ip-cdt:20030829

    DO - 10.1049/ip-cdt:20030829

    M3 - Conference article

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    SP - 303

    EP - 312

    JO - IEE Proceedings - Computers and digital Techniques

    JF - IEE Proceedings - Computers and digital Techniques

    SN - 1350-2387

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