An approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways, is presented. A buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic, is also proposed. Optimisation heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of the approaches.
|Journal||IEE Proceedings - Computers and digital Techniques|
|Publication status||Published - 2003|
|Event||2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany|
Duration: 3 Mar 2003 → 7 Mar 2003
|Conference||2003 Design, Automation and Test in Europe Conference and Exposition|
|Period||03/03/2003 → 07/03/2003|