Abstract
We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.
Original language | English |
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Title of host publication | 2003 Design, Automation and Test in Europe Conference and Exhibition |
Publication date | 2003 |
Edition | 6 |
Pages | 184-189 |
ISBN (Print) | 0769518702 |
DOIs | |
Publication status | Published - 2003 |
Event | 2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany Duration: 3 Mar 2003 → 7 Mar 2003 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html |
Conference
Conference | 2003 Design, Automation and Test in Europe Conference and Exposition |
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Country/Territory | Germany |
City | Munich |
Period | 03/03/2003 → 07/03/2003 |
Internet address |