Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Paul Pop; Petru Eles; Zebo Peng

doi:10.1109/DATE.2003.1253606

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Paul Pop, Petru Eles, Zebo Peng

Linköping University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

Original language	English
Title of host publication	2003 Design, Automation and Test in Europe Conference and Exhibition
Publication date	2003
Edition	6
Pages	184-189
ISBN (Print)	0769518702
DOIs	https://doi.org/10.1109/DATE.2003.1253606
Publication status	Published - 2003
Event	2003 Design, Automation and Test in Europe Conference and Exposition - Munich, Germany Duration: 3 Mar 2003 → 7 Mar 2003 http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

Conference

Conference	2003 Design, Automation and Test in Europe Conference and Exposition
Country/Territory	Germany
City	Munich
Period	03/03/2003 → 07/03/2003
Internet address	http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html

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title = "Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems",

abstract = "We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.",

author = "Paul Pop and Petru Eles and Zebo Peng",

year = "2003",

doi = "10.1109/DATE.2003.1253606",

language = "English",

isbn = "0769518702",

pages = "184--189",

booktitle = "2003 Design, Automation and Test in Europe Conference and Exhibition",

edition = "6",

note = "2003 Design, Automation and Test in Europe Conference and Exposition, DATE 2003 ; Conference date: 03-03-2003 Through 07-03-2003",

url = "http://www.informatik.uni-trier.de/~ley/db/conf/date/date2003.html",

}

Pop, P, Eles, P & Peng, Z 2003, Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. in 2003 Design, Automation and Test in Europe Conference and Exhibition. 6 edn, pp. 184-189, 2003 Design, Automation and Test in Europe Conference and Exposition, Munich, Germany, 03/03/2003. https://doi.org/10.1109/DATE.2003.1253606

TY - GEN

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AU - Pop, Paul

AU - Eles, Petru

AU - Peng, Zebo

PY - 2003

Y1 - 2003

N2 - We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

AB - We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

U2 - 10.1109/DATE.2003.1253606

DO - 10.1109/DATE.2003.1253606

M3 - Article in proceedings

SN - 0769518702

SP - 184

EP - 189

BT - 2003 Design, Automation and Test in Europe Conference and Exhibition

T2 - 2003 Design, Automation and Test in Europe Conference and Exposition

Y2 - 3 March 2003 through 7 March 2003

ER -

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

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