Abstract
Message passing using a network-on-chip (NoC) is an efficient way to provide core-to-core communication on a multicore processor. However, many NoCs use routers and network interfaces that are optimized for the average case. Therefore, it is hard to bound the worst-case latency of a message or the bandwidth. Furthermore, often large buffers are used in the routers and network interfaces, which require a considerable amount of area. This paper presents a statically scheduled NoC that uses timedivision multiplexing at the links, the routers, and the network interfaces. Static scheduled traffic allows computing upper bounds for end-to-end latencies of messages, which is a requirement for building multicore real-time systems. Furthermore, this static scheduled NoC needs no additional buffers, except pipeline registers, and the resulting resource requirement is low.
| Original language | English |
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| Title of host publication | Proceedings of the 12th International Workshop on Network on Chip Architectures |
| Number of pages | 6 |
| Publisher | Association for Computing Machinery |
| Publication date | 2019 |
| ISBN (Print) | 978-1-4503-6949-7 |
| DOIs | |
| Publication status | Published - 2019 |
| Event | 12th International Workshop on Network on Chip Architectures - Columbus, United States Duration: 13 Oct 2019 → 13 Oct 2019 Conference number: 12 |
Conference
| Conference | 12th International Workshop on Network on Chip Architectures |
|---|---|
| Number | 12 |
| Country/Territory | United States |
| City | Columbus |
| Period | 13/10/2019 → 13/10/2019 |
Keywords
- Real-time systems
- Network-on-chip
- Time-predictable computer architecture