S4NOC: a Minimalistic Network-on-Chip for Real-Time Multicores

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Message passing using a network-on-chip (NoC) is an efficient way to provide core-to-core communication on a multicore processor. However, many NoCs use routers and network interfaces that are optimized for the average case. Therefore, it is hard to bound the worst-case latency of a message or the bandwidth. Furthermore, often large buffers are used in the routers and network interfaces, which require a considerable amount of area. This paper presents a statically scheduled NoC that uses timedivision multiplexing at the links, the routers, and the network interfaces. Static scheduled traffic allows computing upper bounds for end-to-end latencies of messages, which is a requirement for building multicore real-time systems. Furthermore, this static scheduled NoC needs no additional buffers, except pipeline registers, and the resulting resource requirement is low.
Original languageEnglish
Title of host publicationProceedings of the 12th International Workshop on Network on Chip Architectures
Number of pages6
PublisherAssociation for Computing Machinery
Publication date2019
ISBN (Print)978-1-4503-6949-7
Publication statusPublished - 2019
Event12th International Workshop on Network on Chip Architectures - Columbus, United States
Duration: 13 Oct 201913 Oct 2019
Conference number: 12


Conference12th International Workshop on Network on Chip Architectures
Country/TerritoryUnited States


  • Real-time systems
  • Network-on-chip
  • Time-predictable computer architecture


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