RTTM: Real-Time Transactional Memory

Martin Schoeberl; Florian Brandner; Jan Vitek

doi:10.1145/1774088.1774158

RTTM: Real-Time Transactional Memory

Martin Schoeberl
, Florian Brandner
, Jan Vitek

TU Wien
Purdue University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor. © 2010 ACM.
Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor

Original language	English
Title of host publication	Proceedings of the 25th ACM Symposium on Applied Computing
Publisher	Association for Computing Machinery
Publication date	2010
Pages	326-333
ISBN (Print)	978-16-05-58638-0
DOIs	https://doi.org/10.1145/1774088.1774158
Publication status	Published - 2010
Externally published	Yes
Event	25th Annual ACM Symposium on Applied Computing - Sierre, Switzerland Duration: 22 Mar 2010 → 26 Mar 2010 Conference number: 25

Conference

Conference	25th Annual ACM Symposium on Applied Computing
Number	25
Country/Territory	Switzerland
City	Sierre
Period	22/03/2010 → 26/03/2010

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10.1145/1774088.1774158

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title = "RTTM: Real-Time Transactional Memory",

abstract = "Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor. {\textcopyright} 2010 ACM. Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor",

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year = "2010",

doi = "10.1145/1774088.1774158",

language = "English",

isbn = "978-16-05-58638-0",

pages = "326--333",

booktitle = "Proceedings of the 25th ACM Symposium on Applied Computing",

publisher = "Association for Computing Machinery",

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note = "25th Annual ACM Symposium on Applied Computing, ACM SAC 2010 ; Conference date: 22-03-2010 Through 26-03-2010",

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AU - Brandner, Florian

AU - Vitek, Jan

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N2 - Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor. © 2010 ACM. Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor

AB - Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor. © 2010 ACM. Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor

U2 - 10.1145/1774088.1774158

DO - 10.1145/1774088.1774158

M3 - Article in proceedings

SN - 978-16-05-58638-0

SP - 326

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BT - Proceedings of the 25th ACM Symposium on Applied Computing

PB - Association for Computing Machinery

T2 - 25th Annual ACM Symposium on Applied Computing

Y2 - 22 March 2010 through 26 March 2010

ER -

RTTM: Real-Time Transactional Memory

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