Abstract
Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems we are interested in worst-case execution times. We propose real-time transactional memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. We define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor. © 2010 ACM.
Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor
Keyword: Worst-case execution time,Real time systems,transactional memory,Multiprocessing systems,Transactional memory,Synchronization,Adaptive systems,Average case,Lock-based synchronization,real-time systems,Storage allocation (computer),Chip Multiprocessor
| Original language | English |
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| Title of host publication | Proceedings of the 25th ACM Symposium on Applied Computing |
| Publisher | Association for Computing Machinery |
| Publication date | 2010 |
| Pages | 326-333 |
| ISBN (Print) | 978-16-05-58638-0 |
| DOIs | |
| Publication status | Published - 2010 |
| Externally published | Yes |
| Event | 25th Annual ACM Symposium on Applied Computing - Sierre, Switzerland Duration: 22 Mar 2010 → 26 Mar 2010 Conference number: 25 |
Conference
| Conference | 25th Annual ACM Symposium on Applied Computing |
|---|---|
| Number | 25 |
| Country/Territory | Switzerland |
| City | Sierre |
| Period | 22/03/2010 → 26/03/2010 |