Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration

Alberto Nannarelli, M. Re, Gian Carlo Cardarilli, L. Di Nunzio, M. Spaziani Brunella, R. Fazzolari, F. Carbonari

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over-clocking the configuration bitstream circuitry beyond the limits stated in the specifications of these standard blocks. The experimental results show that the most power efficient implementation can
reach a throughput of about 780 MB/s, corresponding to a configuration latency of about 670 micro-seconds for bitstreams of 1.2 MB. We also investigate alternatives to boost the reconfiguration throughput and sketch a methodology to achieve the most power efficient implementation of FPGA-based accelerators.
Original languageEnglish
Title of host publicationProceedins of the 30th IEEE International System-on-Chip Conference
Number of pages5
Publication date2017
Publication statusPublished - 2017
Event30th IEEE International System-on-Chip Conference - München, Germany
Duration: 5 Sep 20178 Sep 2017


Conference30th IEEE International System-on-Chip Conference

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