RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution

    Research output: Contribution to conferenceConference abstract for conferenceResearchpeer-review

    50 Downloads (Pure)
    Original languageEnglish
    Publication date2017
    Publication statusPublished - 2017
    Event43rd International conference on Micro and Nano Engineering - Braga, Portugal
    Duration: 18 Sep 201722 Sep 2017
    Conference number: 43

    Conference

    Conference43rd International conference on Micro and Nano Engineering
    Number43
    CountryPortugal
    CityBraga
    Period18/09/201722/09/2017

    Keywords

    • Plasma etching
    • Bosch process
    • RIE-lag
    • Scallops

    Cite this

    @conference{915aefd7e44641f390e82eb381285c5f,
    title = "RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution",
    keywords = "Plasma etching, Bosch process, RIE-lag, Scallops",
    author = "Bingdong Chang and Pele Leussink and Flemming Jensen and J{\"o}rg H{\"u}bner and Henri Jansen",
    year = "2017",
    language = "English",
    note = "43rd International conference on Micro and Nano Engineering, MNE 2017 ; Conference date: 18-09-2017 Through 22-09-2017",

    }

    Chang, B, Leussink, P, Jensen, F, Hübner, J & Jansen, H 2017, 'RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution' 43rd International conference on Micro and Nano Engineering, Braga, Portugal, 18/09/2017 - 22/09/2017, .

    RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution. / Chang, Bingdong; Leussink, Pele; Jensen, Flemming; Hübner, Jörg; Jansen, Henri.

    2017. Abstract from 43rd International conference on Micro and Nano Engineering, Braga, Portugal.

    Research output: Contribution to conferenceConference abstract for conferenceResearchpeer-review

    TY - ABST

    T1 - RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution

    AU - Chang, Bingdong

    AU - Leussink, Pele

    AU - Jensen, Flemming

    AU - Hübner, Jörg

    AU - Jansen, Henri

    PY - 2017

    Y1 - 2017

    KW - Plasma etching

    KW - Bosch process

    KW - RIE-lag

    KW - Scallops

    M3 - Conference abstract for conference

    ER -

    Chang B, Leussink P, Jensen F, Hübner J, Jansen H. RIE-lag “Correction” in Bosch Etch Process of Silicon to Enable Profile Straightness and Improved Scallop Size Distribution. 2017. Abstract from 43rd International conference on Micro and Nano Engineering, Braga, Portugal.