Research of Power Loop Layout and Parasitic Inductance in GaN Transistor Implementation

Bainan Sun, Kasper Lüthje Jørgensen, Zhe Zhang, Michael A. E. Andersen

Research output: Contribution to journalJournal articleResearchpeer-review

Abstract

Power loop is critical in the PCB layout consideration. Especially for high frequency GaN transistor applications, low inductance power loop design is needed to guarantee the switching reliability and the operation efficiency. Finite element analysis (FEA) is generally used in the power loop inductance
quantification, which is time consuming and impractical for parameters sweep. In this paper, a numerical equation for power loop inductance estimation is given based on the novel loop inductance model. The power loop inductance can be estimated in a fast approximation approach. A minimal layout method is proposed to reduce the power loop inductance for the GaN transistor application. The impact of power loop inductance is discussed over the two operation modes of the synchronous buck converter. A modular buck converter prototype is designed to demonstrate the effectiveness of the given numerical equation and validate the lower power loop inductance by the proposed layout.
Original languageEnglish
JournalIEEE Transactions on Industry Applications
Number of pages10
ISSN0093-9994
Publication statusAccepted/In press - 2021

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