Research of PCB Parasitic Inductance in the GaN Transistor Power Loop

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Gallium Nitride (GaN) transistor in the high power density converter application is widely researched nowadays. High frequency switching largely reduces the volume of passive components and also leads to challenges in the PCB layout. Parasitic inductance within the critical power loop should be minimized to fully harness the potential of GaN transistor fast switching capability. This paper provides a numerical method for the power loop inductance quantification. Experimental results
on the synchronous buck converter are given to validate the estimation accuracy.
Original languageEnglish
Title of host publicationProceedings of IEEE Workshop on Wide Bandgap Power Devices and Applications
Number of pages5
PublisherIEEE
Publication date2019
ISBN (Print)9781728121451
DOIs
Publication statusPublished - 2019
EventIEEE Workshop on Wide Bandgap Power Devices and Applications in Asia 2019 - Howard International House, Taipei, Taiwan, Province of China
Duration: 23 May 201925 May 2019
http://www.wipda-asia2019.org/

Workshop

WorkshopIEEE Workshop on Wide Bandgap Power Devices and Applications in Asia 2019
LocationHoward International House
CountryTaiwan, Province of China
CityTaipei
Period23/05/201925/05/2019
Internet address
CitationsWeb of Science® Times Cited: No match on DOI

    Research areas

  • Power loop inductance, GaN transistor, Finite element analysis

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